TMS320C51 datasheet(31/87 Pages) TI

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TMS320C5x, TMS320LC5x

DIGITAL SIGNAL PROCESSORS

SPRS030A – APRIL 1995 – REVISED APRIL 1996

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

host port interface (continued)

The HPI has two modes of operation, shared-access mode (SAM) and host-only mode (HOM). In SAM, the

normal mode of operation, both the ’C57S /’LC57 and the host can access HPI memory. In this mode,

asynchronous host accesses are resynchronized internally and, in case of conflict, the host has access priority

and the ’C57S /’LC57S waits one cycle. Host and CPU accesses to the HPI memory can be resychronized

through polling of a command word or through interrupts to prevent stalling the CPU for one cycle. The HOM

capability allows the host to access HPI memory while the ’C57S /’LC57 is in IDLE2 mode (all internal clocks

stopped) or in reset mode. The external ’C57S /’LC57S clock even can be stopped. The host can, therefore,

access the HPI RAM while the ’C57S /’LC57 is in its optimum configuration in terms of power consumption.

The HPI control register has two data strobes, HDS1 and HDS2, a read / write strobe HR / W, and an address

strobe HAS, to enable a glueless interface to a variety of industry-standard host devices. The HPI is easily

interfaced to hosts with multiplexed address /data bus, separate address and data buses, one data strobe, and

a read / write strobe, or two separate strobes for read and write. An HPI-ready pin, HRDY, is provided to specify

wait states for hosts that support an asynchronous input. When the ’C57S /’LC57 operating frequency is

variable, or when the host is capable of accessing at a faster rate than the maximum shared-access mode

access rate, the HRDY pin provides a convenient way to adjust the host access rate automatically (no software

handshake needed) to a change in the ’C57S /’LC57 clock rate or an HPI-mode switch.

The HPI supports high-speed back-to-back accesses. In the shared-access mode, the HPI can handle one byte

every five ’C57S /’LC57 periods (that is, 64 Mb/s with a 40-MHz ’C57S /’LC57). The HPI is designed so that the

host can take advantage of this high bandwidth and run at frequencies up to (f

n) ÷ 5, where n is the number

of host cycles for an external access and f is the ’C57S /’LC57 frequency. In host-only mode, the HPI supports

even higher speed back-to-back host accesses: 1 byte every 50 ns (that is, 160 Mb/s) independently of the

’C57S /’LC57 clock rate.

serial ports

The ’C5x provides high-speed full-duplex serial ports that allow direct interface to other ’C5x devices, codecs,

and other devices in a system. There is a general-purpose serial port, a time-division-multiplexed (TDM) serial

port, and an auto-buffered serial port (BSP).

The general-purpose serial port uses two memory-mapped registers for data transfer: the data-transmit register

(DXR) and the data-receive register (DRR). Both registers can be accessed in the same manner as any other

memory location. The transmit and receive sections of the serial port each have associated clocks,

frame-synchronization pulses, and serial shift registers, and serial data can be transferred either in bytes or in

16-bit words. Serial port receive and transmit operations can generate their own maskable transmit and receive

interrupts (XINT and RINT), allowing serial port transfers to be managed by way of software. The ’C5x serial

ports are double-buffered and fully static.

The TDM port allows the device to communicate through time-division multiplexing with up to seven other ’C5x

devices with TDM ports. Time-division multiplexing is the division of time intervals into a number of subintervals

with each subinterval representing a prespecified communications channel. The TDM port serially transmits

16-bit words on a single data line ( TDAT ) and destination addresses on a single address line ( TADD). Each

device can transmit data on a single channel and receive data from one or more of the eight channels providing

a simple and efficient interface for multiprocessing applications. A frame synchronization pulse occurs once

every 128 clock cycles corresponding to transmission of one 16-bit word on each of the eight channels. Like

the general-purpose serial port, the TDM port is double-buffered on both input and output data. The TDM port

also can be configured in software to operate as a general-purpose serial port as described above. Both types

of ports are capable of operating at up to one-fourth the machine cycle rate (CLKOUT1).

The buffered serial port (BSP) consists of a full-duplex double-buffered serial port interface (SPI) and an

auto-buffering unit (ABU). The SPI block of the BSP is an enhanced version of the general-purpose serial port.

The auto-buffering unit allows the SPI to read / write directly to ’C5x internal memory using a dedicated bus

independently of the CPU. This results in minimum overhead for SPI transactions and faster data rates.

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