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TMS320C51 Datasheet(PDF) 67 Page - Texas Instruments |
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TMS320C51 Datasheet(HTML) 67 Page - Texas Instruments |
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67 / 87 page  TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 67 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 EXTERNAL DMA switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Note 7) (see Figure 21) PARAMETER ’320C5x-40 ’320C5x-57 ’320LC5x-40 ’320LC5x-50 ’320C5x-80 ’320LC5x-80 ’320C5x-100 UNIT MIN MAX MIN MAX MIN MAX td(HOL-HAL) Delay time, HOLD low to HOLDA low 4H † 4H † 4H † ns td(HOH-HAH) Delay time, HOLD high before HOLDA high 2H 2H 2H ns th(AZ-HAL) Address high-impedance before HOLDA low‡ H–15§ H–10§ H–8§ ns ten(HAH-Ad) Enable time, HOLDA high to address driven H–5§ H–4§ H–3§ ns td(XBL-IQL) Delay time, XBR low to IAQ low 4H§ 6H§ 4H§ 6H§ 4H§ 6H§ ns td(XBH-IQH) Delay time, XBR high to IAQ high 2H§ 4H§ 2H§ 4H§ 2H§ 4H§ ns td(XSL-RDV) Delay time, read data valid after XSTRB low 40 29 25 ns th(XSH-RD) Hold time, read data valid after XSTRB high 0 0 0 ns ten(IQL-RDd) Enable time, IAQ low to read data driven¶ 0§ 2H§ 0§ 2H§ 0§ 2H§ ns th(XRL-DZ) Hold time, XR / W low to data high impedance 0§ 15§ 0§ 10§ 0§ 8 ns th(IQH-DZ) Hold time, IAQ high to data high impedance H§ H§ H§ ns ten(D-XRH) Enable time, data from XR / W going high 4§ 3§ 2§ ns † HOLD is not acknowledged until current external access request is complete. ‡ This parameter includes all memory control lines. § Values derived from characterization data and not tested ¶ This parameter refers to the delay between the time the condition (IAQ = 0 and XR / W = 1) is satisfied and the time that the ’C5x data lines become valid. NOTE 7: X preceding a name refers to external drive of the signal. timing requirements over recommended ranges of supply voltage and operating ambient-air temperature (see Note 7) (see Figure 21) ’320C5x-40 ’320C5x-57 ’320LC5x-40 ’320LC5x-50 ’320C5x-80 ’320LC5x-80 ’320C5x-100 UNIT MIN MAX MIN MAX MIN MAX td(HAL-XBL) Delay time, HOLDA low to XBR low# 0§ 0§ 0§ ns td(IQL-XSL) Delay time, IAQ low to XSTRB low# 0§ 0§ 0§ ns tsu(AV-XSL) Setup time, Xaddress valid before XSTRB low 15 12 10 ns tsu(DV-XSL) Setup time, Xdata valid before XSTRB low 15 12 10 ns th(XSL-D) Hold time, Xdata hold after XSTRB low 15 12 10 ns th(XSL-WA) Hold time, write Xaddress hold after XSTRB low 15 12 10 ns tw(XSL) Pulse duration, XSTRB low 45 40 35 ns tw(XSH) Pulse duration, XSTRB high 45 40 35 ns tsu(RW-XSL) Setup time, R / W valid before XSTRB low 20 20 18 ns th(XSH-RA) Hold time, read Xaddress after XSTRB high 0 0 0 ns § Values derived from characterization data and not tested # XBR, XR / W, and XSTRB lines must be pulled up with a 10-k Ω resistor to be certain that they are in an inactive high state during the transition period between the ’C5x driving them and the external circuit driving them. NOTE 7: X preceding a name refers to external drive of the signal. |
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