TMS320C51 datasheet(71/87 Pages) TI

71 / 87 page

TMS320C5x, TMS320LC5x

DIGITAL SIGNAL PROCESSORS

SPRS030A – APRIL 1995 – REVISED APRIL 1996

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

SERIAL-PORT TRANSMIT TIMING, INTERNAL CLOCKS, AND INTERNAL FRAMES

(SEE NOTE 8)

switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Figure 24)

PARAMETER

’320C5x-40

’320C5x-57

’320LC5x-40

’320LC5x-50

’320C5x-80

’320C5x-100

’320LC5x-80

UNIT

MIN

TYP

MAX

MIN

TYP

MAX

td(CX-FX)

Delay time, CLKX rising edge to FSX

–5

–4

td(CX-DX)

Delay time, CLKX rising edge to DX

tdis(CX-DX)

Disable time, CLKX rising edge to DX

40†

29†

tc(SCK)

Cycle time, serial-port clock

tf(SCK)

Fall time, serial-port clock

tr(SCK)

Rise time, serial-port clock

tw(SCK)

Pulse duration, serial-port clock low / high

4H – 20

4H – 14

th(CXH-DXV)

Hold time, DX valid after CLKX high

–5

–4

† Values derived from characterization data and not tested

NOTE 8: Internal clock with external FSX and vice versa are also allowable. However, FSX timings to CLKX always are defined depending on

the source of FSX, and CLKX timings always are dependent on the source of CLKX. Specifically, the relationship of FSX to CLKX is

independent of the source of CLKX.

Bit

FSX

CLKX

th(CXH-DXV)

tr(SCK)

tf(SCK)

tw(SCK)

tc(SCK)

td(CX-FX)

td(CX-DX)

tdis(CX-DX)

tw(SCK)

8/16

7 /15

Figure 24. Serial-Port Transmit Timing of Internal Clocks and Internal Frames

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