TMS320C51 datasheet(35/87 Pages) TI

35 / 87 page

TMS320C5x, TMS320LC5x

DIGITAL SIGNAL PROCESSORS

SPRS030A – APRIL 1995 – REVISED APRIL 1996

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

addressing modes (continued)

In immediate addressing, the actual operand data is provided in a portion of the instruction word or words. There

are two types of immediate addressing: long and short. In short-immediate addressing, the data is contained

in a portion of the bits in a single-word instruction. In long-immediate addressing, the data is contained in the

second word of a two-word instruction. The immediate-addressing mode is useful for data that does not need

to be stored or used more than once during the course of program execution, such as initialization values,

constants, etc.

The register-addressing mode uses operands in CPU registers either explicitly, such as with a direct reference

to a specific register, or implicitly, with instructions that intrinsically reference certain registers. In either case,

operand reference is simplified because 16-bit values can be used without specifying a full 16-bit operand

address or immediate value.

Memory-mapped addressing provides the convenience of easy access to memory-mapped registers located

on page zero of data memory. The flexibility of memory-mapped addressing results because accesses are

made independently of actual DP value and without having to provide a complete address of the memory

location being accessed. Commonly used on-board registers can be accessed with a simplified addressing

scheme.

Circular addressing is the most sophisticated ’C5x addressing mode. This addressing mode allows specified

buffers in memory to be accessed sequentially with a pointer that automatically wraps around to the beginning

of the buffer when the last location is accessed. A total of two independent circular buffers can be allocated at

any given time.

Five dedicated registers are allocated for implementation of circular addressing: a beginning-of-buffer and an

end-of-buffer register for each of the two independent circular buffers and a control register. Additionally, one

of the auxiliary registers is used as the pointer into the circular buffer. All registers used in circular addressing

must be initialized properly prior to performing any circular buffer access.

The circular-addressing mode allows implementation of circular buffers, which facilitate data structures used

in FIR filters, convolution and correlation algorithms, and waveform generators. Having the capability to access

circular buffers automatically with no overhead allows these types of data structures to be implemented most

efficiently.

repeat feature

The repeat function can be used with instructions such as multiply/accumulates (MAC and MACD), block moves

(BLDD and BLPD), I/O transfers (IN/OUT ), and table read/writes (TBLR/TBLW ). These instructions, although

normally multicycle, are pipelined when the repeat feature is used, and they effectively become single-cycle

instructions. For example, the table-read instruction may take three or more cycles to execute, but when the

instruction is repeated, a table location can be read every cycle.

The repeat counter (RPTC) is a 16-bit register that, when loaded with a number N, causes the next single

instruction to be executed N + 1 times. The RPTC register is loaded by either the RPT or the RPTZ instruction,

resulting in a maximum of 65,536 executions of a given instruction. RPTC is cleared by reset. The RPTZ

instruction clears both ACC and PREG before the next instruction starts repeating. Once a repeat instruction

(RPT or RPTZ ) is decoded, all interrupts including NMI (except reset) are masked until the completion of the

repeat loop. However, the device responds to the HOLD signal while executing an RPT/ RPTZ loop.

repeat feature (continued)

The ’C5x implements a block-repeat feature that provides zero-overhead looping for implementation of FOR

and DO loops. The function is controlled by three registers (PASR, PAER, and BRCR) and the BRAF bit in the

PMST register. The block-repeat counter register (BRCR) is loaded with a loop count of 0 to 65,535. Then,

execution of the RPTB (repeat block) instruction loads the program-address-start register (PASR) with the

address of the instruction following the RPTB instruction and loads the program-address-end register (PAER)

TMS320C51 Datasheet(PDF) 35 Page - Texas Instruments

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