TMS320C51 datasheet(63/87 Pages) TI

63 / 87 page

TMS320C5x, TMS320LC5x

DIGITAL SIGNAL PROCESSORS

SPRS030A – APRIL 1995 – REVISED APRIL 1996

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

READY TIMING FOR EXTERNALLY-GENERATED WAIT STATES

timing requirements over recommended ranges of supply voltage and operating ambient-air

temperature (see Note 5) (see Figure 17 and Figure 18)

’320C5x-40

’320C5x-57

’320LC5x-40

’320LC5x-50

’320C5x-80

’320LC5x-80

’320C5x-100

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

tsu(RY-COH)

Setup time, READY before CLKOUT1 rising edge

tsu(RY-RDL)

Setup time, READY before RD falling edge

th(COH-RYH)

Hold time, READY after CLKOUT1 rising edge

th(RDL-RY)

Hold time, READY after RD falling edge

th(WEL-RY)

Hold time, READY after WE falling edge

H + 5

H + 4

H + 3

tv(WEL-RY)

Valid time, READY after WE falling edge

H – 15

H – 10

H – 8

NOTE 5: The external READY input is sampled only after the internal software wait states are completed.

READY

A0 – A15

CLKOUT1

Wait State

Generated

by READY

Wait State

Generated

Internally

th(RDL-RY)

tsu(RY-COH)

th(COH-RYH)

tsu(RY-RDL)

Figure 17. Ready Timing for Externally-Generated Wait States During an External Read Cycle

READY

A0 – A15

CLKOUT1

Wait State Generated by READY

th(COH-RYH)

tsu(RY-COH)

th(WEL-RY)

tv(WEL-RY)

Figure 18. Ready Timing for Externally-Generated Wait States During an External Write Cycle

TMS320C51 Datasheet(PDF) 63 Page - Texas Instruments

TMS320C51 Datasheet(HTML) 63 Page - Texas Instruments

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