TMS320C51 datasheet(75/87 Pages) TI

75 / 87 page

TMS320C5x, TMS320LC5x

DIGITAL SIGNAL PROCESSORS

SPRS030A – APRIL 1995 – REVISED APRIL 1996

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

BUFFERED SERIAL-PORT TRANSMIT TIMING OF EXTERNAL FRAMES (SEE NOTES 9 AND 10)

switching characteristics over recommended operating conditions (see Figure 28)

PARAMETER

MIN

MAX

UNIT

td(CXH-DXV)

Delay time, DX valid after CLKX rising edge

tdis(CXH-DX)

Disable time, DX invalid after CLKX rising edge

tdis(CXH-DX)PCM

Disable time in PCM mode, DX invalid after CLKX rising edge

ten(CXH-DX)PCM

Enable time in PCM mode, DX valid after CLKX rising edge

th(CXH-DXV)

Hold time, DX valid after CLKX rising edge

timing requirements over recommended operating conditions (see Figure 28)

MIN

MAX

UNIT

tc(SCK)

Cycle time, serial-port clock

†

tf(SCK)

Fall time, serial-port clock

4‡

tr(SCK)

Rise time, serial-port clock

4‡

tw(SCK)

Pulse duration, serial-port clock low/high

8.5

tsu(FX-CXL)

Setup time, FSX before CLKX falling edge

th(CXL-FX)

Hold time, FSX after CLKX falling edge

tc(SCK)–5§

† The serial-port design is fully static and, therefore, can operate with tc(SCK) approaching ∞. It is characterized approaching an input frequency

of 0 Hz but tested at a much higher frequency to minimize test time.

‡ Values derived from characterization data and not tested

§ If the FSX pulse does not meet this specification, the first bit of the serial data is driven on the DX pin until FSX goes low (sampled on falling edge

of CLKX). After falling edge of the FSX, data is shifted out on the DX pin.

NOTE 9: Internal clock with external FSX and vice versa are also allowable. However, FSX timings to CLKX always are defined depending on

the source of FSX, and CLKX timings always are dependent upon the source of CLKX. Specifically, the relationship of FSX to CLKX

is independent of the source of CLKX. External FSX timings are obtained from the “timing requirements over recommended operating

conditions” table listed in the “Buffered Serial-Port Transmit Timing of External Frames” section and internal FSX timings are obtained

from the “switching characteristics over recommended operating conditions” table listed under the “Buffered Serial-Port Transmit Timing

of Internal Frame and Internal Clock” section. Internal CLKX timings are obtained from the “switching characteristics over recommended

operating conditions” table listed under the “Buffered Serial-Port Transmit Timing of Internal Frame and Internal Clock” section and

external CLKX timings are obtained from the “timing requirements over recommended operating conditions” table in the “Buffered

Serial-Port Transmit Timing of External Frames” section.

NOTE 10: Timings for CLKX and FSX are given with polarity bits (CLKP and FSP) set to 0

DX BIt

FSX

CLKX

8/16

7/15

th(CXH-DXV)

td(CXH-DXV)

tw(SCK)

tr(SCK)

tf(SCK)

tw(SCK)

tc(SCK)

th(CXL-FX)

tdis(CXH-DX)

tsu(FX-CXL)

Figure 28. Buffered Serial-Port Transmit Timing of External Clocks and External Frames

TMS320C51 Datasheet(PDF) 75 Page - Texas Instruments

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