INA233 datasheet(21/48 Pages) TI1

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Frame 1 SMBus ALERT Response Address Byte

Frame 2 Slave Address Byte

(1)

Start By

Master

ACK By

Slave

From

Slave

NACK By

Master

Stop By

Master

SDA

SCL

ALERT

R/W

Frame 1 Slave Address Byte

(1)

Frame 2 PMBus Command Code

Start By

Master

ACK By

Slave

ACK By

Slave

ACK By

Master

SDA

SCL

Frame 3 Slave Address Byte

Frame 5 Data Byte 1

Stop by

Master

SDA

SCL

Frame N+4 Data Byte N

No ACK By

Master

ACK By

Master

Frame 4 Number of

Bytes = N

ACK By

Master

Repeated Start

By Master

R/W

INA233

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A block read is similar to the read word format in that first the device is written to with the desired PMBus

command that is to return the desired value. This write is accomplished by issuing a slave address byte with the

R/W bit low, followed by the PMBus command code. The master then generates a repeated START condition

and sends the slave address byte with the R/W bit high to initiate the read command. The next byte is

transmitted by the slave is the total number of bytes that are sent to the master. This byte is followed by an

Acknowledge (ACK) from the master; then the slave transmits the first data byte. At the end of each byte the

master sends an Acknowledge and the next byte is sent by the slave. The master can terminate data transfer by

generating a Not-Acknowledge after receiving any data byte, or by generating a START or STOP condition.

Figure 28 shows the block read operation timing diagram. Figure 29 shows the timing diagram for the SMBus

Alert response operation.

The value of the slave address byte is determined by the settings of the A0 and A1 pins; see Table 2.

Figure 28. Timing Diagram for Block Read Format

(1)

The value of the slave address byte is determined by the settings of the A0 and A1 pins; see Table 2.

Figure 29. Timing Diagram for SMBus ALERT Response

7.5.6.3.1

Packet Error Checking

The INA233 supports packet error checking as described in the SMBus version 3.0 specification. Packet error

checking is a method to improve the reliably and communication robustness of the digital interface. Packet error

checking is implemented by appending a packet error code (PEC) at the end of each message transfer. To

maximize compatibly, devices that support packet error checking must be able to communicate with the host and

other devices that do not support the error checking protocol. Therefore, packet error checking can help improve

the communication robustness when desired but is optional when not supported by the master or other devices

on the bus. See the SMBus version 3.0 specification for additional details on implementing packet error checking

in an SMBus environment.

INA233 Datasheet(PDF) 21 Page - Texas Instruments

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