PC87303 datasheet(24/114 Pages) NSC

24 / 114 page

20 Configuration Registers (Continued)

Bit 1

EPP version select bit When this bit is 0 Version

17 is supported and STB AFD INIT and SLIN

are open drain outputs

When this bit is 1 Version 19 is supported (IEEE

1284) and STB AFD INIT and SLIN are push-pull

outputs This bit has the same affect on the output

buffers in ECP modes 0 and 2

Bit 2

ECP enabIe bit When this bit is 0 the ECP is dis-

abled and in power-down mode The ECP registers

are not accessible (access ignored) and the ECP

interrupt and DMA are inactive When this bit is 1

the ECP is enabled The software should change

this bit to 1 only when bits 0 1 and 2 of the exist-

ing CTR are 1 0 and 0 respectively

Bit 3

ECP clock freeze control bit

In power-down

modes 2 and 3 When this bit is 0 the clock provid-

ed to the ECP is stopped and

When this bit is 1 the clock provided to the ECP is

not stopped

Bit 4

Reserved This bit must be set to 0

Bit 5

Parallel port interrupt (IRQ5 or IRQ7) polarity con-

trol bit When this bit is 0 the interrupt polarity is

level high or negative pulse When this bit is 1 the

interrupt polarity is inverted

Bit 6

Parallel port interrupt (IRQ5 or IRQ7) open drain

control bit When this bit is 0 the configured inter-

rupt line (IRQ5 or IRQ7) has a totem-pole output

When this bit is 1 the configured interrupt line has

an open drain output (drive low no drive high no

internal pullup)

Bit 7

RTC RAM write mask bit When this bit is 0 the

RTC RAM is writeable When this bit is 1 the RTC

RAM is not writeable and writes are ignored

256 KBC and RTC Control Register

(KRR Index e 05h)

This register enables and disables the keyboard controller

(KBC) and the Real-Time Clock (RTC) It selects the clock

source and operating mode of the KBC selects different

banks of CMOS RAM in the RTC and selects the RTC test

mode

When PWRGOOD is low

KRR is initialized to

00000001

Bit 0

KBC Enable bit When this bit is zero the KBC

clock is frozen and the state of its dedicated pins

cannot be altered When this bit is one the KBC is

functional

Bit 1

KBC Speed control bit Controls the KBC speed

when X1OSC clock source is selected (KRR7 is

0) This bit is ignored when SYSCLK clock source

is selected (KRR7 is 1)

When this bit is 0 the KBC clock is the X1OSC

frequency divided by three (typically 8 MHz) When

this bit is 1 the KBC clock is the X1OSC frequen-

cy divided by two (typically 12 MHz)

Bit 2

PAE Program Access Enable of the keyboard

controller This bit should be set to 1

Bit 3

RTC Enable bit When this bit is 0 the RTC is dis-

abled and IRQ8 is in TRI-STATE When this bit is 1

the RTC is enabled

Bit 4

CLKTEST RTC clock test mode select When this

bit is 1 the SYNC pin outputs the 32 kHz RTC

clock When this bit is 0 the SYNC pin is not driv-

en When PWRGOOD is low this bit is initialized to

Bit 5

RAMSREL RTC CMOS RAM bank select When

this bit is 1 it selects the upper 128 bytes of CMOS

RAM When this bit is 0 it selects the lower

128 bytes of CMOS RAM

Bit 6

On-chip KBC Address Decoder Enable bit When

this bit is 0 (and KRR0 is 1) the KBC is accessed

when CS is low and the address pin A2 selects

the KBC registers When this bit is 1 (and KRR0 is

1) the CS input is ignored and the address pins

A0 – 9 select the KBC registers (60h or 64h)

Bit 7

KBC clock source select bit When this bit is 0 the

KBC uses the X1OSC clock source When this bit

is 1 the KBC uses the SYSCLK clock source This

bit enables the KBC to operate in power-down

mode even when the X1 clock is frozen It may be

modified only when the KBC is disabled via bit 0 of

KRR

257 Power Management Control Register

(PMC Index e 06h)

This register controls the TRI-STATE and input pins The

PMC register is accessed through Index 06h The PMC Reg-

ister is cleared to 0 on reset

Bit 0

IDE TRI-STATE Control bit

0 When this bit is 0 it does not affect the IDE

pins

1 IDE7 and HCS01 are in TRI-STATE IDEHI and

IDELO are inactive when either the IDE is dis-

abled or the chip is in power-down mode

Bit 1

FDC TRI-STATE Control bit

0 When this bit is 0 it does not affect the FDC

pins

1 The

FDC

outputs

except

IRQ6

are

TRI-STATE when either the FDC is disabled or

the chip is in power down mode

Bit 2

UART TRI-STATE Control bit

0 When this bit is 0 it does not affect the UART’s

pins

1 The outputs of any UART except IRQ4 and

IRQ3 are in TRI-STATE when that UART is dis-

abled or the chip is in power-down

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