PC87303 datasheet(71/114 Pages) NSC

71 / 114 page

60 Serial Ports (Continued)

Bit 3

This bit enables the interrupt when set No exter-

nal pin is associated with this bit other than IRQ3

4 In Local Loopback Mode this bit controls bit 7

of the MODEM Status Register

Bit 4

This bit provides a Local loopback feature for diag-

nostic testing of the UART When it is set to 1 the

following changes take place the transmitter Seri-

al Output (SOUT) is set to the Marking (1) state

the receiver Serial Input (SIN) is disconnected the

output of the Transmitter Shift Register is ‘‘looped

back’’ (connected) to the Receiver Shift Register

the four MODEM Control inputs (DSR CTS RI

and DCD) are disconnected and the DTR RTS

OUT1 IRQ ENABLE bits in MCR are internally

connected to DSR CTS RI and DCD in MSR re-

spectively The MODEM Control output pins are

forced to their high (inactive) states In the Loop-

back Mode data that is transmitted is immediately

received This feature allows the processor to veri-

fy the transmit-and-received-data paths of the seri-

al port

In the Loopback Mode the receiver and transmit-

ter interrupts are fully operational The MODEM

Status Interrupts are also operational but the in-

terrupts’ sources are the lower four bits of MCR

instead of the four MODEM control inputs Writing

a 1 to any of these 4 MCR bits will cause an inter-

rupt In Loopback Mode the interrupts are still con-

trolled by the Interrupt Enable Register The IRQ3

and IRQ4 pins will be at TRI-STATE in the Loop-

back Mode

Bits 5 – 7

These bits are permanently set to 0

TABLE 6-5 PC87303 Interrupt Control Functions

Interrupt

Interrupt Set and Reset Functions

Identification

Bit 3

Bit 2

Bit 1

Bit 0

Priority

Level

Interrupt Type

Interrupt Source

Interrupt Reset

Control

(FIFO

Mode

Only)

None

Highest

Receiver Line

Overrun Error Parity Error

Reading the Line

Status

Framing Error or Break Interrupt

Status Register

Second

Received Data

Receiver Data Available

Read Receiver Buffer

Available

Second

Character

No Characters Have Been

Reading the Receiver

(FIFO

Time-Out

Removed from or input to the

Buffer Register

Mode

Indication

RCVR FIFO During the Last 4

Only)

Character Times and there is at

least 1 Character in it during this

Time

Third

Transmitter Holding

Reading the IIR Register

(if Source of Interrupt) or

Writing the Transmitter

Holding Register

Fourth

MODEM Status

Clear to Send or Data Set

Reading the MODEM

Ready or Ring Indicator or

Status Register

Data Carrier Detect

PC87303 Datasheet(PDF) 71 Page - National Semiconductor (TI)

PC87303 Datasheet(HTML) 71 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL