PC87303 datasheet(5/114 Pages) NSC

5 / 114 page

List of Figures

FIGURE 2-1

PC87303 Configuration Registers

FIGURE 2-2

PC87303 Four Floppy Drive Circuit

FIGURE 3-1

FDC Functional Block Diagram

FIGURE 4-1

FDC Command Structure

FIGURE 4-2

IBM Perpendicular and ISO Formats Supported by Format Command

FIGURE 5-1

FDC Data Separator Block Diagram

FIGURE 5-2

PC87303 Dynamic Window Margin Performance

FIGURE 5-3

Read Data AlgorithmState Diagram

FIGURE 5-4

Perpendicular Recording Drive RW Head and Pre-Erase Head

FIGURE 6-1

PC87303 Composite Serial Data

FIGURE 6-2

Receiver FIFO Trigger Level

FIGURE 7-1

EPP 17 Address Write

FIGURE 7-2

EPP 17 Address Read

FIGURE 7-3

EPP Write with ZWS

FIGURE 7-4

EPP 19 Address Write

FIGURE 7-5

EPP 19 Address Read

FIGURE 7-6

ECP Forward Write Cycle

FIGURE 7-7

ECP Backward Read Cycle

FIGURE 8-1

IDE Interface Signal Equations (Non-DMA)

FIGURE 9-1

Keyboard Controller Functional Block Diagram

FIGURE 9-2

Keyboard Controller to Host System Interface

FIGURE 9-3

Status Register

FIGURE 9-4

PSW Register Bits

FIGURE 9-5

Keyboard Controller Data Memory Map

FIGURE 9-6

Keyboard Controller Stack Organization

FIGURE 9-7

Active Pull-Up IO Port Structure

FIGURE 9-8

Using Port Pins as Inputs

FIGURE 9-9

Timing Generation and Timer Circuit

FIGURE 9-10

Internal Clock Connection

FIGURE 9-11

External Clock Connection

FIGURE 9-12

Instruction Cycle Timing

FIGURE 9-13

Oscillator Internal and External Circuitry

FIGURE 9-14

InterruptStatus Timing

FIGURE 9-15

Typical Battery Configuration

FIGURE 9-16

Typical Battery Current During Battery Backed Mode

FIGURE 10-1

Clock Timing

FIGURE 10-2

Microprocessor Read Timing

101

FIGURE 10-3

Microprocessor Write Timing

101

FIGURE 10-4

Read after Write Operation to All Registers and RAM Timing

101

FIGURE 10-5

Baud Out Timing

102

FIGURE 10-6

Transmitter Timing

102

FIGURE 10-7

Sample Clock Timing

103

FIGURE 10-8

Receiver Timing

103

FIGURE 10-9

FIFO Mode Receiver Timing

103

FIGURE 10-10

Timeout Receiver Timing

104

FIGURE 10-11

MODEM Control Timing

104

FIGURE 10-12a FDC DMA Timing

105

FIGURE 10-12b ECP DMA Timing

106

PC87303 Datasheet(PDF) 5 Page - National Semiconductor (TI)

PC87303 Datasheet(HTML) 5 Page - National Semiconductor (TI)

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