PC87303 datasheet(76/114 Pages) NSC

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70 Parallel Port (Continued)

The software must write zero to bits 0 1 and 3 of the CTR

controlled by these bits are controlled by hardware during

EPP access Once these bits are written with zero the soft-

ware may issue multiple EPP access cycles The software

must set bit 7 of the PTR register to 1 if bit 5 of CTR is to

control direction

To meet the EPP 19 specifications the software should

change direction (bit 5 of CTR) only when bit 7 of STR is 1

(ie change direction at EPP Idle Phase as defined in the

IEEE 1284 document)

When bit 7 of PTR is 0 EPP cycles to the external device

are generated by invoking read or write cycles to the EPP

When bit 7 of PTR is 1

1 Reading an EPP register during forward direction (bit 5 of

CTR is 0) is allowed only in EPP 17 It returns the register

latched value (not the PD0 – 7 pins’ value) and does not

generate an EPP read cycle

2 Writing to an EPP register during backward direction (bit 5

of CTR is 1) updates the register data and does not gen-

erate an EPP write cycle

EPP 17 Address Write

The following procedure selects a peripheral device or reg-

ister See also

Figure 7-1

1 The host writes a byte to the EPP address register WR

goes low to latch D0 – D7 into the address register The

latch drives the address register onto PD0 – 7 and the

EPP pulls WRITE low

2 The EPP pulls ASTRB low to indicate that data has been

sent

3 If WAIT is low during the host write cycle IOCHRDY

goes low

When WAIT goes high the EPP pulls IOCHRDY high

4 When IOCHRDY goes high it causes WR to go high If

WAIT is high during the host write cycle then the EPP

does not pull IOCHRDY to low

5 When WR goes high it causes the EPP to pull WRITE

and ASTRB to high

Only when WRITE and ASTRB are high can the EPP

change PD0 – 7

TLC12074 – 31

FIGURE 7-1 EPP 17 Address Write

EPP 17 Address Read

The following procedure reads from the address register

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