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PC87303 Datasheet(PDF) 52 Page - National Semiconductor (TI) |
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PC87303 Datasheet(HTML) 52 Page - National Semiconductor (TI) |
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52 / 114 page  40 FDC Command Set Description (Continued) Execution Phase Internal registers are written Result Phase None READ DATA Command Phase MT MFM SK 0 0 1 1 0 IPS X X X X HD DR1 DR0 Track Number Drive Head Number Sector Number Bytes per Sector End of Track Sector Number Intersector Gap Length Data Length Execution Phase Data read from disk drive is transferred to system via DMA or Non-DMA modes Result Phase Status Register 0 Status Register 1 Status Register 2 Track Number Head Number Sector Number Bytes per Sector READ DELETED DATA Command Phase MT MFM SK 0 1 1 0 0 IPS X X X X HD DR1 DR0 Track Number Drive Head Number Sector Number Bytes per Sector End of Track Sector Number Intersector Gap Length Data Length Execution Phase Data read from disk drive is transferred to system via DMA or Non-DMA modes Result Phase Status Register 0 Status Register 1 Status Register 2 Track Number Head Number Sector Number Bytes per Sector READ ID Command Phase 0 MFM 0 0 1 0 1 0 X X XXXHDDR1 DR0 Execution Phase Controller reads first ID Field header bytes it can find and reports these bytes to the system in the result bytes Result Phase Status Register 0 Status Register 1 Status Register 2 Track Number Head Number Sector Number Bytes per Sector READ A TRACK Command Phase 0 MFM 0 0 0 0 1 0 IPS X X X X HD DR1 DR0 Track Number Drive Head Number Sector Number Bytes per Sector End of Track Sector Number Intersector Gap Length Data Length Execution Phase Data read from disk drive is transferred to system via DMA or non-DMA modes Result Phase Status Register 0 Status Register 1 Status Register 2 Track Number Head Number Sector Number Bytes per Sector RECALIBRATE Command Phase 000001 1 1 000000DR1 DR0 Execution Phase Disk drive head is stepped out to Track 0 Result Phase None 52 |
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