PC87303 datasheet(33/114 Pages) NSC

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30 FDC Register Description (Continued)

D6 – 3

Reserved

Always 1

D2 – 1

Data Rate Select 10

These bits indicate the

status of the DRATE1 – 0 bits programmed through

the DSR or CCR

High Density

This bit is low when the 1 Mbps or

500 kbps data rate is chosen and high when the

300 kbps or 250 kbps data rate is chosen This bit is

independent of the IDENT value

DIRModel 30 Mode

D6 D5 D4

DESC

DSKCHG

DMAEN NOPRE DRATE1 DRATE0

RESET

COND

Disk Changed

Active low status of DSKCHG disk

interface input During power-down this bit is invalid

if it is read by the software

D6 – 4

Reserved

Always 0

DMA Enable

Active high status of the DMAEN bit

in the DOR

No Precompensation

Active high status of the

NOPRE bit in the CCR

D1 – 0

Data Rate Select 10

These bits indicate the

status of the DRATE 10 bits programmed through

the DSRCCR

319 Configuration Control Register (CCR)

Write Only

This is the write-only data rate register commonly used in

PC-AT applications This register is not affected by a soft-

ware reset and is set to 250 kbps after a hardware reset

The data rate of the floppy controller is determined by the

last write to either the CCR or DSR

CCRPC-AT and PS2 Modes

DESC

000000

DRATE1

DRATE0

RESET

COND

D7 – 2

Reserved

Should be set to 0

D1 – 0

Data Rate Select 10

These bits determine the

data rate of the floppy controller See Table 3-8 for

the appropriate values

CCRModel 30 Mode

DESC

NOPRE

DRATE1

DRATE0

RESET

COND

D7 – 3

Reserved

Should be set to 0

No Precompensation

This bit can be set by soft-

ware but it has no functionality It can be read by bit

D2 of the DIR when in the Model 30 register mode

Unaffected by a software reset

D1 – 0

Data Rate Select 10

These bits determine the

data rate of the floppy controller See Table 3-8 for

the appropriate values

32 RESULT PHASE STATUS REGISTERS

The Result Phase of a command contains bytes that hold

status information The format of these bytes is described

below Do not confuse these status bytes with the Main

Status Register which is a read only register that is always

valid The Result Phase status registers are read from the

Data Register (FIFO) only during the Result Phase of certain

commands (see Section 41 Command Set Summary) The

status of each register bit is indicated when the bit is a 1

321 Status Register 0 (ST0)

DESC

HDS

DS1

DS0

RESET

COND

D7 – 6

Interrupt Code

00 e Normal Termination of Command

01 e Abnormal Termination of Command Execu-

tion of command was started but was not

successfully completed

10 e Invalid Command Issued Command issued

was not recognized as a valid command

11 e Internal drive ready status changed state dur-

ing the drive polling mode Only occurs after a

hardware or software reset

Seek End

Seek Relative Seek or Recalibrate

command completed by the controller (Used during

a Sense Interrupt command)

Equipment Check

After a Recalibrate command

Track 0 signal failed to occur (Used during Sense

Interrupt command)

Not Used Always 0

Head Select

Indicates the active high status of the

HDSEL pin at the end of the Execution Phase

D1 – 0

Drive Select 10

These two binary encoded bits

indicate the logical drive selected at the end of the

Execution Phase

00 e Drive 0 selected

01 e Drive 1 selected

10 e Drive 2 selected

11 e Drive 3 selected

322 Status Register 1 (ST1)

DESC

RESET

COND

End of Track

Controller transferred the last byte of

the last sector without the TC pin becoming active

The last sector is the End of Track sector number

programmed in the Command Phase

Not Used Always 0

PC87303 Datasheet(PDF) 33 Page - National Semiconductor (TI)

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