PC87303 datasheet(32/114 Pages) NSC

32 / 114 page

30 FDC Register Description (Continued)

TABLE 3-7 Default Precompensation Delays

Data Rate

Precompensation Delay

1 Mbps

417 ns

500 kbps

1250 ns

300 kbps

1250 ns

250 kbps

1250 ns

D1 0

Data Rate Select 10

These bits determine the

data rate for the floppy controller See Table 3-8 for

the corresponding data rate for each value of D1

D0 The data rate select bits are unaffected by a

software reset and are set to 250 kbps after a hard-

ware reset

TABLE 3-8 Data Rate Select Encoding

Data Rate Select

Data Rate

MFM

1 Mbps

Illegal

500 kbps

250 kbps

300 kbps

150 kbps

250 kbps

125 kbps

Note

FM mode is not guaranteed by functional testing

317 Data Register (FIFO)

ReadWrite

The FIFO (readwrite) is used to transfer all commands

data and status between the mP and the FDC During the

Command Phase the mP writes the command bytes into the

FIFO after polling the RQM and DIO bits in the MSR During

the Result Phase the mP reads the result bytes from the

FIFO after polling the RQM and DIO bits in the MSR

Enabling the FIFO and setting the FIFO threshold is done

via the Configure command If the FIFO is enabled only the

Execution Phase byte transfers use the 16 byte FIFO The

FIFO is always disabled during the Command and Result

Phases of a controller operation A software reset will not

disable enabled FIFO if the LOCK bit is set in the Lock

Command After a hardware reset the FIFO is disabled to

maintain compatibility with PC-AT systems

The 16-byte FIFO can be used for DMA Interrupt or soft-

ware polling type transfers during the execution of a read

write format or scan command In addition the FIFO can

be put into a Burst or Non-Burst mode with the Mode com-

mand In the Burst mode FDRQ or IRQ6 remains active

until all of the bytes have been transferred to or from the

FIFO In the Non-Burst mode FDRQ or IRQ6 is deasserted

for 350 ns to allow higher priority transfer requests to be

serviced The Mode command can also disable the FIFO for

either reads or writes separately The FIFO allows the sys-

tem a larger latency without causing a disk over-

rununderrun error The FIFO is typically used with multi-

tasking operating systems andor when running systems at

or above a 1 Mbps data rate In its default state the FIFO is

disabled and contains a zero threshold The default state is

entered after a hardware reset

Data Register (FIFO)

DESC

Data 70

RESET

Byte Mode

COND

During the Execution Phase of a command involving data

transfer tofrom the FIFO the system must respond to a

data transfer service request based on the following formu-

Maximum Allowable Data Transfer Service Time

(THRESH a 1) c 8 c tDRP b (16 c tICP)

This formula is good for all data rates with the FIFO enabled

or disabled THRESH is a four bit value programmed in the

Configure command which sets the FIFO threshold If the

FIFO is disabled THRESH is zero in the above formula The

last term of the formula (16 c tICP) is an inherent delay due

to the microcode overhead required by the FDC This delay

is also data rate dependent See Table 9-1 for the tDRP and

tICP times See Section 1122 for a description of tDRP and

tICP

The programmable FIFO threshold (THRESH) is useful in

adjusting the floppy controller to the speed of the system In

other words a slow system with a sluggish DMA transfer

capability uses a high value of THRESH giving the system

more time to respond to a data transfer service request

(FDRQ for DMA mode or IRQ6 for Interrupt mode) Con-

versely a fast system with quick response to a data transfer

service request would use a low value of THRESH

318 Digital Input Register (DIR)

Read Only

This diagnostic register is used to detect the state of the

DSKCHG disk interface input and some diagnostic signals

The function of this register depends on its mode of opera-

tion When in the PC-AT mode the D6 – D0 are TRI-STATE

to avoid conflict with the fixed disk status register at the

same address DIR is unaffected by a software reset

DIRPC-AT Mode

DESC

DSKCHG

XXXXXXX

RESET

COND

Disk Changed

Active high status of DSKCHG disk

interface input During power-down this bit is invalid

if it is read by the software

D6 – 0

Unused

by the FDC (at TRI-STATE) The bits are

used by the Hard Disk Controller Status Register

DIRPS2 Mode

DESC

DSKCHG

DRATE1

DRATE0

HIGH

DEN

RESET

COND

Disk Changed

Active high status of DSKCHG disk

interface input During power-down this bit is invalid

if it is read by the software

PC87303 Datasheet(PDF) 32 Page - National Semiconductor (TI)

PC87303 Datasheet(HTML) 32 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL