PC87303 datasheet(87/114 Pages) NSC

87 / 114 page

90 Keyboard Controller and Real-Time Clock (Continued)

P24 – P27 can be used to enhance the interface to the host

system P24 and P25 can be used to reflect the state of the

OBF and IBF flags respectively in the STATUS register us-

ing the ‘‘EN FLAGS’’ instruction After executing this in-

struction P24 reflects the value of the OBF pin and P25

reflects the value of the IBF pin Data written to P24 and

P25 serve as a mask to the output Whena1is written P24

outputs the state of the OBF flag and P25 outputs the com-

plement state of the IBF flag When 0 is written the output

is forced to zero These OBF and IBF pins can be used as

the interrupt requests to the host system for data transfer

handshaking

The ‘‘EN DMA’’ instruction configures P26 and P27 as DRQ

and DACK pins After executing this instruction P26 and

P27 can be utilized for DMA transfers between the host

system and the PC87303 P26 goes active when 1 is written

to it It can be used as the DRQ to the host system When

P27 which is connected to the DACK of the system is pulled

active data can be read or written through D0 – D7 hence

completing the DMA cycle P26 is reset to zero when P27 is

pulled active or the ‘‘EN DMA’’ instruction is executed The

latter case allows the PC87303 to abort a DMA request

912 Program Memory

The keyboard controller of the PC87303 has a 2kx8ROM

based program memory An 10-bit program counter allows

direct access to every location of the program memory

Fig-

ure 9-4 shows the memory map There are three special

locations associated with hardware functions

1 000h After the keyboard controller is reset the program

counter is initialized to 000h

TLC12074 – 40

FIGURE 9-4 Keyboard Controller Data Memory Map

2 003h When the input buffer of the host interface (DBBlN)

is full and the IBF interrupt is enabled the CPU

makes an interrupt call to this location

3 007h When the timer overflows and the timer interrupt is

enabled the CPU makes an interrupt call to this

location

913 Data Memory and Registers

The keyboard controller has 256 Bytes of data memory in-

cluding 2 banks of registers 8 registers each and an 8-level

stack

Figure 9-4 shows the data RAM organization

RAM locations 0h – 7h are used as register bank0 They are

designated as R0 – R7 respectively Register bank1 (R0 –

R7 ) are located in 18h – 1Fh of the address map Bank0 is

the default register bank when the chip comes out from re-

set Bank switching is accomplished by using ‘‘register bank

select’’ instructions (SEL RB0 SEL RB1) Locations 8h –

17h are reserved for the stack Each stack entry consists of

2 bytes

Figure 9-5 shows the organization of the stack The

stack pointer in the PSW register points to the top of the

stack A0inthe stack pointer corresponds to RAM loca-

tions 8h and 9h

TLC12074 – 41

FIGURE 9-5 Keyboard Controller Stack Organization

PC87303 Datasheet(PDF) 87 Page - National Semiconductor (TI)

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