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PC87303 Datasheet(PDF) 77 Page - National Semiconductor (TI) |
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PC87303 Datasheet(HTML) 77 Page - National Semiconductor (TI) |
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77 / 114 page  70 Parallel Port (Continued) 2 The EPP first pulls WRITE low and then pulls ASTRB low to indicate that data has been sent 3 If WAIT is high during the host write cycle ZWS goes low and IOCHRDY goes high 4 When the host pulls WR high the EPP pulls ASTRB ZWS and WRITE to high Only when WRlTE and ASTRB are high can the EPP change PD0 – 7 5 If the peripheral is fast enough to pull WAIT low before the host terminates the write cycle the EPP pulls IOCHRDY to low but does not pull ZWS to low thus carrying out a normal (non-ZWS EPP 17) write opera- tion Note A read operation is similar except for the data direction and the activation of RD instead of WR EPP Zero Wait State (ZWS) Data WriteRead Operation (both 17 and 19) An EPP 17 and 19 Zero Wait State data writeread opera- tion is similar to the EPP Zero Wait State address writeread operation with the exception that the data strobe (DSTRB signal) and a data register replace the address strobe (ASTRB signal) and the address register respectively See Figure 7-3 TLC12074 – 33 FIGURE 7-3 EPP Write with ZWS EPP 19 Address Write The following procedure selects a peripheral or register See also Figure 7-4 1 The host writes a byte to the EPP address register 2 The EPP pulls IOCHRDY low and waits for WAIT to go low 3 When WAIT goes low the EPP pulls WRITE to low drives the latched byte onto PD0 – PD7 If WAIT was already low steps 2 and 3 occur concurrent- ly 4 The EPP pulls ASTRB low and waits for WAIT to go high 5 When WAIT goes high the EPP stops pulling IOCHRDY low pulls ASTRB high and waits for WAIT to go low 6 Only if no EPP write is pending when WAIT goes low (or when bit 7 of PTR is 1 and the direction is changed to Backwards by setting bit 5 of CTR to 1) the EPP pulls WRITE to high If an EPP write is pending WRITE remains low and the EPP may change PD0 – PD7 TLC12074 – 34 FIGURE 7-4 EPP 19 Address Write EPP 19 Address Read The following procedure reads from the address register See also Figure 7-5 1 The host reads a byte from the EPP address register When RD goes low the EPP pulls IOCHRDY low and waits for WAIT to go low 77 |
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