PC87303 datasheet(10/114 Pages) NSC

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10 Pin Description

TABLE 1-1 Pin Descriptions (Alphabetical)

Symbol

Function

A10–A0

46–56

Address

These address lines from the microprocessor determine which internal register is

accessed A0 – A10 are don’t cares during an DMA transfer A10 is used only during ECP

operations

ACK

125

Acknowledge

This input is pulsed low by a connected printer to indicate that it has received

data from the parallel port This pin has a nominal 25 kX pull-up resistor attached to it (See

DR1 and Table 7-5 for further information)

ADRATE0

Additional Data Rate 0

When selected this output is identical to DRATE0 It is provided in

addition to DRATE0 It reflects the currently selected FDC data rate (bit 0 in the Configuration

Control Register (CCR) or the Data Rate Select Register (DSR) whichever was written to

last) ADRATE0 is configured when bit 0 of Advanced SuperIO Configuration Register (ASC)

is 1 (See IRQ5 for further information)

AFD

116

Automatic Feed XT

When this signal is low the printer should automatically line feed after

each line is printed This pin is in a TRI-STATE condition 10 ns aftera0is loaded into the

corresponding Control Register bit The system should pull this pin high using a 47 kX

resistor (See DSTRB and Table 7-5 for further information)

AEN

Address Enable

This input disables function selection via A10 – A0 when it is high Access

during DMA transfer is NOT affected by this pin

ASTRB

119

Address Strobe

This signal is used in Enhanced Parallel Port (EPP) mode as an address

strobe It is active low (See SLIN and Table 7-5 for further information)

BADDR01

86 89

Base Address

These CMOS inputs are sensed during reset to determine one of four base

addresses from which the Index and Data Registers are offset (see Table 2-2) An internal

pull-down resistor of 30 kX is present on this pin Use a 10 kX resistor to pull this pin to VDD

(See IDELO HCS0 for further information)

BOUT12

110100

BAUD Output

This multi-function pin provides the associated serial channel Baud Rate

generator output signal when test mode is selected in the Power and Test Configuration

Output (SOUT) function (See SOUT and CFG0 – 4 for further information)

BUSY

124

Busy

This pin is set high by a connected printer when it cannot accept another character It

has a nominal 25 kX pull-down resistor attached to it (See WAIT and Table 7-5 for further

information)

CFG0 – 4

100 103

Configuration on Power-Up

These CMOS inputs select 1 of 32 default configurations in

which the PC87303 powers-up (see Table 2-1) They are provided with CMOS input buffers

108 110

An internal pull-down resistor of 30 kX is present on each pin Use a 10 kX resistor to pull

111

these pins to VDD

Chip Select

Enables the host to access the keyboard controller through D0 – D7 when bit 7

of Chip Select 0 Configuration Register 1 (CS0CF1) is 0 (See CS0 for further information)

CSOUT

Chip Select Read Output

This is the data buffer output enable pin It indicates any read from

the PC87303 except for IDE accesses This signal is valid when bit 2 of PTR is 1 CSOUT is

not active during read in PC-AT mode from registers 3F7 and 377 CSOUT is not active when

the read is from a disabled module (See PWDN for further information)

CTS12

109 99

Clear to Send

When low this indicates that the MODEM or data set is ready to exchange

data The CTS signal is a MODEM status input whose condition the CPU can test by reading

bit 4 (CTS) of the MODEM Status Register (MSR) for the appropriate serial channel Bit 4 is

the complement of the CTS signal Bit 0 (DCTS) of the MSR indicates whether the CTS input

has changed state since the previous reading of the MSR CTS has no effect on the

transmitter

Note

Whenever the DCTS bit of the MSR is set an interrupt is generated if MODEM Status interrupts are enabled

CS01

2 23

Programmable Chip Select

CS01 are programmable chip select andor enable andor

output enable signals that can be used for a game port IO port expander or other add-on

peripheral The decoded address and the assertion conditions are configured via the

PC87303 configuration registers 0Ah – 0Dh When either of these two pins is acting as CS01

output enable the PC87303 assumes the relevant input is 1 (See SYSCLK and CS for further

information)

D7 – D0

33 34 35 36

Data

Bi-directional data lines to the microprocessor D0 is the LSB and D7 is the MSB These

signals all have 24 mA (sink) buffered outputs

37 38 39 42

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