PC87303 datasheet(82/114 Pages) NSC

82 / 114 page

70 Parallel Port (Continued)

78 SOFTWARE CONTROLLED DATA TRANSFER

(Modes 000 and 001)

Software controlled data transfer is supported in modes 000

and 001 The software generates peripheral-device cycles

by modifying the DATAR and DCR registers and reading the

DSR DCR and DATAR registers The negotiation phase

and nibble mode transfer as defined in the IEEE 1284 stan-

dard are performed in these modes

In these modes the FIFO is reset (empty) and is not func-

tional the DMA and RLE are idle

Mode 000 is for the forward direction only the direction bit

is forced to 0 and PD0 – 7 are driven Mode 001 is for both

the forward and backward directions The direction bit con-

trols whether PD0 – 7 are driven

79 AUTOMATIC DATA TRANSFER (Modes 010 and 011)

Automatic data transfer (ECP cycles generated by hard-

ware) is supported only in modes 010 and 011 Automatic

DMA access to fill or empty the FIFO is supported in modes

010 011 and 110 Mode 010 is for the forward direction

only The direction bit is forced to 0 and PD0 – 7 are driven

Mode 011 is for both the forward and backward directions

The direction bit controls whether PD0 – 7 are driven

Automatic Run Length Expanding (RLE) is supported in the

backward direction

Note 1

FIFO-full condition is checked before every expanded byte push

Note 2

A pending DMA request is removed and a pending RLE expansion

is aborted when you switch from modes 010 or 011 to other

modes

Note 3

The two FIFO ports are neither synchronized nor linked together

except via the empty and full FIF0 status bits The FIFO shall not

delay the push and pop operations even when they are performed

concurrently Care must be taken not to corrupt PD0–PD7 or D0–7

while the other FIFO port is accessed

Note 4

In the forward direction the empty bit is updated when the ECP

cycle is completed not right after the last byte is popped out of the

FIFO (valid cleared on cycle end)

Note 5

ZWS is not asserted for DMA cycles

Note 6

The one-bit commanddata tag is used only in forward direction

791 Forward Direction (bit 5 of DCR e 0)

When the ECP is in forward direction and the FIFO is not full

(bit 1 of ECR is 0) the FIFO can be filled by software writes

to the FlFO registers (AFIFO and DFIFO in mode 011 and

CFIFO in mode 010)

When DMA is enabled (bit 3 of ECR is 1 and bit 2 of ECR is

0) the ECP automatically issues DMA requests to fill the

FIFO with normal data byte

When the ECP is in forward direction and the FIFO is not

empty (bit 0 of ECR is 0) the ECP pops a byte from the FIFO

and issues write cycle to the peripheral device The ECP

drives AFD according to the operation mode (ECR bits 5 – 7)

and according to the tag of the popped byte as follows In

Parallel Port FIFO mode (mode 010) AFD is controlled by bit

1 of DCR In ECP mode (mode 011) AFD is controlled by the

popped tag AFD is driven high for normal data byte and

driven low for command byte

792 ECP Forward Write Cycle

An ECP write cycle starts when the ECP drives the popped

tag onto AFD and the popped byte onto PD0 – 7 When

BUSY is low the ECP asserts STB In 010 mode the ECP

deasserts STB to terminate the write cycle In 011 mode the

ECP waits for BUSY to be high before it deasserts STB

When BUSY is high the ECP deasserts STB and changes

AFD and PD0 – 7 only after BUSY is low

TLC12074 – 36

FIGURE 7-6 ECP Forward Write Cycle

793 Backward Direction (bit 5 of DCR is 1)

When the ECP is in the backward direction and the FIFO is

not full (bit 1 of ECR is 0) the ECP issues a read cycle from

the peripheral device and monitors the BUSY signal If

BUSY is high the byte is a data byte and it is pushed into the

FIFO If BUSY is low the byte is a command byte The ECP

checks bit 7 of the command byte if it is high the byte is

ignored if it is low the byte is tagged as an RLC byte (not

pushed into the FIFO but used as a Run Length Count to

expand the next byte read) Following an RLC read the ECP

issues a read cycle from the peripheral device to read the

data byte to be expanded This byte is considered a data

byte regardless of its BUSY state (even if it is low) This

byte is pushed into the FIFO (RLC a 1) times (ie

RLC e 0 push the byte once RLC e 127 push the byte

128 times)

When the ECP is in the backward direction and the FIFO is

not empty (bit 0 of ECR is 0) the FIFO can be emptied by

software reads from the FIFO register (only DFIFO in mode

011 no AFIFO and CFIFO read)

When DMA is enabled (bit 3 of ECR is 1 and bit 2 of ECR is

0) the ECP automatically issues DMA requests to empty the

FIFO (only in mode 011)

794 ECP Backward Read Cycle

An ECP read cycle starts when the ECP drives AFD low

The peripheral device drives BUSY high for a normal data

read cycle or drives BUSY low for a command read cycle

and drives the byte to be read onto PD0 – 7

When ACK is asserted the ECP drives AFD high When AFD

is high the peripheral device deasserts ACK The ECP reads

the PD0 – 7 byte then drives AFD low When AFD is low the

peripheral device may change BUSY and PD0 – 7 states in

preparation for the next cycle

TLC12074 – 37

FIGURE 7-7 ECP Backward Read Cycle

PC87303 Datasheet(PDF) 82 Page - National Semiconductor (TI)

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