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PC87303 Datasheet(PDF) 84 Page - National Semiconductor (TI) |
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PC87303 Datasheet(HTML) 84 Page - National Semiconductor (TI) |
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84 / 114 page  80 Integrated Device Electronics Interface (IDE) (Continued) The IDE Interface Circuit has some additional IDE DMA sup- port When bit 1 of FCR is 1 the PC87303 IDE responds to a DMA acknowledgement on the IDEACK input pin as fol- lows a) IDEL0 is asserted when IDEACK is asserted and either RD or WR is asserted b) IDED7 is functional (ie read IDED7 to D7 write D7 to IDED7) when IDEACK is asserted and either RD or WR is asserted c) HCS10 are not asserted on DMA cycles The equations shown in Figure 8-1 define the signals of the PC87303 IDE pins Equations Comments HCS0 e A9 A8 A7 A6 A5 A4 A3 AEN Active at 1F0 – 1F7 HCS1 e A9 A8 A7 A6 A5 A4 A3 A2 A1 AEN Active at 3F6 3F7 IDELO e HCS0 (RD a WR) a HCS1 (WR A0) a RD Write 1F0 – 1F7 3F6 Read 1F0 – 1F7 3F6 3F7 IDEHI e IOCS16 HCS0 (RD a WR) Read or Write 1F0 – 1F7 in AT Mode IDED7 (read) e (HCS0 RD) a (HCS1 A0) RD Provides D7 during Read 1F0 – 1F7 and 3F6 IDED7 (write) e WR HCS0 a (HCS1 A0) Provides D7 during Write 1F0 – 1F7 and 3F6 FIGURE 8-1 IDE Interface Signal Equations (Non-DMA) 84 |
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