PC87303 datasheet(22/114 Pages) NSC

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20 Configuration Registers (Continued)

TABLE 2-4 Primary and Secondary

Drive Address Selection

Bit 5

Bit 7

Drive

PC-AT Mode

FDC

Primary

3F0–7h

FDC

Secondary

3F0–7h

IDE

Primary

1F0 – 7 3F6 3F7h

IDE

Secondary

170 – 7 376 7h

252 Function Address Register (FAR Index e 01h)

This register selects the ISA IO address range to which

each peripheral function responds

Bits 01

These bits select the parallel port address as

shown in Table 2-5

TABLE 2-5 Parallel Port Addresses

ASC

FAR

Parallel

PC-AT

Bit 0

Bit 1

Bit 0

Port

Interrupt

Address

LPTB (378 – 37F)

IRQ5 (Note)

LPTA (3BC – 3BE)

IRQ7

LPTC (278 – 27F)

IRQ5

Reserved

TRI-STATE

(CTR4 e 0)

LPTB (378 – 37F)

IRQ7

LPTC (278 – 27F)

IRQ7

Note

The interrupt assigned to this address can be changed to IRQ7 by

setting Bit 3 of the power and test register

Bits 2–5

These bits determine which ISA IO address range

is associated with each UART (see Tables 2-6

2-7)

TABLE 2-6 COM Port Selection for UART1

FAR

UART1

Bit 3

Bit 2

COM

1 (3F8-F)

2 (2F8-F)

3 (Table 2-8)

4 (Table 2-8)

Note

COM3 and COM4 addresses are determined by Bits 6 and 7

TABLE 2-7 COM Port Selection for UART2

FAR

UART2

Bit 5

Bit 4

COM

1 (3F8-F)

2 (2F8-F)

3 (Table 2-8)

4 (Table 2-8)

Note

COM3 and COM4 addresses are determined by Bits 6 and 7

Bits 6 7

These bits select the addresses that are used for

COM3 and COM4 (see Table 2-8)

TABLE 2-8 Address Selection for COM3 and COM4

Bit 7

Bit 6

COM3 IRQ4

COM4 IRQ3

3E8–Fh

2E8–Fh

338–Fh

238–Fh

2E8–Fh

2E0–7h

220–7h

228–Fh

253 Power and Test Register (PTR Index e 02h)

This register determines several power-down features the

power-down method used when the power-down pin

(PWDN) is asserted (crystal and clocks vs clocks only)

whether hardware power-down is enabled and provides a

bit for software power-down of all enabled functions It se-

lects whether IRQ7 or IRQ5 is associated with LPTB It puts

the enabled UARTs into their test mode

Independent of this register the floppy disk controller can

enter low power mode via the Mode Command or the Data

Rate Select Register

Bit 0

Setting this bit causes all enabled functions to be

powered down If the crystal power-down option is se-

lected (see Bit 1) the crystal is also powered down All

stopped

Bit 1

When the power-down pin or Bit 0 is asserted this bit

determines whether the enabled functions have their

internal clocks stopped (Bit 1 e 0) or the external

crystal (Bit 1 e 1) is stopped Stopping the crystal is

the lowest power consumption state of the part How-

ever if the crystal is stopped a finite amount of time

(E8 ms) is required for crystal stabilization once the

power-down pin (PWDN) or Bit 0 is deasserted If all

internal clocks are stopped but the crystal continues

to oscillate no stabilization period is required after the

power-down pin or Bit 0 is deasserted

Bit 2

Setting this bit enables the chip select function of the

PWDN CSOUT pin Resetting this bit enables the

power-down function of this pin Sync pin is sampled

during reset to this bit

PC87303 Datasheet(PDF) 22 Page - National Semiconductor (TI)

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