PC87303 datasheet(72/114 Pages) NSC

72 / 114 page

60 Serial Ports (Continued)

69 MODEM STATUS REGISTER (MSR)

This register provides the current state of the control lines

from the MODEM (or peripheral device) to the CPU In addi-

tion to this current-state information

four bits of the

MODEM Status Register provide change information These

bits are set to a logic 1 whenever a control input from the

MODEM changes state They are reset to logic 0 whenever

the CPU reads the MODEM Status Register Table 6-2

shows the contents of the MSR Details on each bit follow

Bit 0

This bit is the Delta Clear to Send (DCTS) indicator

Bit 0 indicates that the CTS input to the chip has

changed state since the last time it was read by the

CPU

Bit 1

This bit is the Delta Data Set Ready (DDSR) indica-

tor It indicates that the DSR input to the chip has

changed state since the last time it was read by the

CPU

Bit 2

This bit is the Trailing Edge of Ring Indicator (TERI)

detector It indicates that the RI input to the chip has

changed from a low to a high state

Bit 3

This bit is the Delta Data Carrier Detect (DDCD) in-

dicator It indicates that the DCD input to the chip

has changed state

Note

Whenever bit 0 1 2 or 3 is set to logic 1 a MODEM Status

Interrupt is generated

Bit 4

This bit is the complement of the Clear to Send

(CTS) input If bit 4 (loopback) of the MCR is set to a

1 this bit is equivalent to RTS in the MCR

Bit 5

This bit is the complement of the Data Set Ready

(DSR) input If bit 4 of the MCR is set to a 1 this bit

is equivalent to DTR in the MCR

Bit 6

This bit is the complement of the Ring Indicator (RI)

input If bit 4 of the MCR is set to a 1 this bit is

equivalent to OUT1 in the MCR

Bit 7

This bit is the complement of the Data Carrier De-

tect (DCD) input If bit 4 of the MCR is set to a 1 this

bit is equivalent to IRQ ENABLE in the MCR

610 SCRATCHPAD REGISTER (SCR)

This 8-bit ReadWrite Register does not control the UART

in any way It is intended as a scratchpad register to be used

by the programmer to hold data temporarily

70 Parallel Port

71 INTRODUCTION

This parallel interface is designed to provide all of the sig-

nals and registers needed to communicate through a stan-

dard parallel printer port as found in the IBM PC-XT PC-AT

PS2 and Centronics systems This parallel port supports

three standard modes of operation SPP EPP ECP The

Standard Parallel Port (SPP) is a software based protocol

with performance of up to 150 kbps

The Enhanced Parallel Port (EPP) is a hardware protocol

which offers up to 2 Mbps

The Extended Capabilities Port (ECP) is also a hardware

protocol with up to 2 Mbps transfer rate In addition the

ECP has FIFO’s for receive and transmit and DMA support

to reduce the CPU overhead The ECP mode 0 is in fact

compatible with the SPP mode The ECP specification de-

fines the ACDC parameters of the signals to allow fast

communication without termination problems

All the above standards are incorporated into the 1284 IEEE

specifications

The address decoding of the registers utilizing A0 and A1 is

shown in Table 7-1 Table 7-3 shows the Reset states of

Parallel port registers and pin signals These registers are

shown in Section 72 to Section 74

TABLE 7-1 Parallel Interface

Address

Access

Data

ReadWrite

Status

Read

Control

ReadWrite

TRI-STATE

Special circuitry provides protection against damage that

might be caused when the printer is powered but the

PC87303 is not

There are two Standard Parallel Port (SPP) modes of opera-

tion (Compatible and Extended see Table 7-2) two En-

hanced Parallel Port (EPP) modes of operation and one Ex-

tended Capabilities Port (ECP) mode to complete a full IEEE

1284 parallel port

TABLE 7-2 Standard Parallel Port

Modes Selection

Port Function

PTR7

Compatible

Extended

In Compatible mode a write operation causes the data to be

presented on pins PD0 – PD7 A read operation in this mode

causes the Data Register to present the last data written to

it by the CPU See Table 7-3

In the Extended Mode a write operation to the data register

causes the data to be latched If the Data Port Direction bit

(CTR5) is 0 the latched data is presented to the pins if it is

1 the data is only latched When Data Port Direction bit

(CTR5) is 0 a read operation from this register allows the

CPU to read the last data it wrote to the port In the Extend-

ed Mode with the Data Port Direction bit set to 1 (read) a

read from this register causes the port to present the data

on pins PD0 – PD7

TABLE 7-3 SPP Data Register Read and Write Modes

PTR7

CTR5

Result

Data Written to PD0 – 7

Data Read from the Output

Latch

Data Written to PD0 – 7

Data Written is Latched

Data Read from the Output

Latch

Data Read from PD0 – 7

To support a high transfer rate the IO buffers of the paral-

lel port signals require improved impedance matching IEEE

P1284 defines two types of IO buffers Level 1 (standard

IO buffersopen-drain with weak pull-up) and Level 2

(new IO bufferspush-pull with driver impedance and slew

rate according to new standards)

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