PC87303 datasheet(12/114 Pages) NSC

12 / 114 page

10 Pin Description (Continued)

TABLE 1-1 Pin Descriptions (Alphabetical)

(Continued)

Symbol

Function

FDRQ

DMA Request

Active high output to signal the DMA controller that a FDC data transfer is needed

When in PC-AT or Model 30 mode this signal is enabled by bit D3 of the DOR When in PS2 mode

FDRQ is always enabled and bit D3 of the DOR is reserved

HCS0

Hard Drive Chip Select 0

This output is active in the PC-AT mode when 1) the hard drive registers

from 1F0 – 1F7h are selected and the primary address is used or 2) when the hard drive registers from

170 – 177h are selected and the secondary address is used This output is inactive if the IDE interface

is disabled via the Configuration Register (See BADDR1 for further information)

HCS1

Hard Drive Chip Select 1

This output is active in the PC-AT mode when 1) the hard drive registers

from 3F6 – 7 are selected and the primary address is used or 2) the hard drive registers from 376 – 377

are selected and the secondary address is used This output is also inactive if the IDE interface is

disabled via the Configuration Register

HDSEL

Head Select

This output determines which side of the FDD is accessed When Active the head

selects side 1 When inactive the head selects side 0

IDEACK

IDE DMA Acknowledge

This is the IDE DMA acknowledge input pin when bit 1 of FCR is 1 In this

case the DENSEL polarity is active high (IDENT assumed 1) This pin is the IDENT input pin when bit 1

of FCR is 0 (See IDENT pin for further information)

IDED7

IDE Bit 7

This pin provides the data bus bit 7 signal to the IDE hard drive during accesses in the

address range 1F0 – 1F7h 170 – 177h 3F6h and 376h This pin is TRI-STATE during read or write

accesses to 3F7h and 377h

IDEHI

IDE High Byte

This output enables the high byte data latch during a read or write to the hard drive if

the hard drive returns IOCS16 This output is inactive if the IDE interface is disabled via the

Configuration Register (See VLD0 and DRID1 for further information)

IDELO

IDE Low Byte

This output enables the low byte data latch during a read or write to the hard drive This

output is inactive if the IDE interface is disabled via the Configuration Register (See BADDR0 for

further information)

IDENT

Identity

After chip reset the state of IDENT determines the polarity of the DENSEL output When

IDENT is a logic ‘‘1’’ DENSEL is active high for the 500 kbps and 1 Mbps data rates When IDENT is a

logic ‘‘0’’ DENSEL is active low for the 500 kbps and 1 Mbps data rates (See Mode command for

explanation of DENSEL) (See IDEACK for further information)

INDEX

Index

This input signals the beginning of a FDD track

INIT

118

Initialize

When this signal is low it causes a connected printer to be initialized This pin is in a TRI-

STATE condition 10 ns aftera1is loaded into the corresponding Control Register bit The system

should pull this pin high using a 47 kX resistor

IOCHRDY

IO Channel Ready

This is the IO Channel Ready open drain output When IOCHRDY is driven low

the EPP extends the host cycle

IOCS16

IO Chip Select 16-Bit

This input is driven by a connected peripheral device which can accommodate

a 16-bit access This pin is configured when bit 2 of ASC is 0 (See DRID0 for further information)

IRQ34

19 18

Interrupt 3 and 4

These are active high interrupts associated with the serial ports IRQ3 presents the

signal if the serial channel has been designated as COM2 or COM4 IRQ4 presents the signal if the

serial port is designated as COM1 or COM3 The appropriate interrupt goes active whenever it is

enabled via the Interrupt Enable Register (IER) the associated Interrupt Enable bit (Modem Control

available Transmitter Holding Register Empty or a Modem Status Flag is set The interrupt signal is

reset low (inactive) after the appropriate interrupt service routine is executed after being disabled via

the IER or after a Master Reset Either interrupt can be disabled putting them into TRI-STATE by

setting the MCR3 bit low

PC87303 Datasheet(PDF) 12 Page - National Semiconductor (TI)

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