PC87303 datasheet(74/114 Pages) NSC

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70 Parallel Port (Continued)

74 CONTROL REGISTER (CTR)

TLC12074 – 30

This register provides all output signals to control the print-

er Except for bit 5 it is a read and write register

Bit 0

This bit (STB) directly controls the data strobe sig-

nal to the printer via the STB pin This bit is the

inverse of the STB pin

Bit 1

This bit (AFD) directly controls the automatic feed

XT signal to the printer via the AFD pin Setting this

bit high causes the printer to automatically feed

after each line is printed This bit is the inverse of

the AFD pin

Bit 2

This bit (INIT) directly controls the signal to initial-

ize the printer via the INIT pin Setting this bit to

low initializes the printer This bit follows the INIT

Note

This pin must be set to 1 before enabling the EPP or ECP

modes via bits 0 or 2 of the PCR register

Bit 3

This bit (SLIN) directly controls the select in signal

to the printer via the SLIN pin Setting this bit high

selects the printer It is the inverse of the SLIN pin

Bit 4

This bit controls the parallel port generated by the

ACK signal Its function changes slightly depend-

ing on the parallel port mode selected In ECP

mode this bit should be set to 0 In the following

description IRQx indicates either IRQ5 or IRQ7

(based upon PTR3)

Compatible mode

when bit 4 e 0 IRQx is floated

when bit 4 e 1 IRQx follows ACK transitions

Extended mode

when bit 4 e 0 IRQx is floated

when bit 4 e 1 IRQx becomes active on ACK trail-

ing edge

EPP mode

when bit 4 e 0 IRQx is floated

when bit 4 e 1 IRQx is pulsed when ACK is acti-

vated or an EPP timeout occurs

Bit 5

This bit determines the parallel port direction when

bit 7 of PTR is 1 The default condition results in

the parallel port being in the output mode This is a

ReadWrite

bit in EPP mode In SPP mode it is a

write only bit a read from it will return 1 See Table

7-3 for further details

Bits 6 7

Reserved These bits are always 1

Normally when the Control Register is read the bit values

are provided by the internal output data latch These bit

values can be superseded by the logic level of the STB

AFD INIT and SLIN pins if these pins are forced high or

low by an external voltage In order to force these pins high

or low the corresponding bits should be set to their inactive

state (eg AFD e STB e SLIN e 0 INIT e 1) See Table

7-4

TABLE 7-4 Parallel Port Reset States

Signal

Reset Control

State after Reset

SLIN

TRI-STATE

INIT

Zero

AFD

TRI-STATE

STB

TRI-STATE

IRQ5 7

TRI-STATE

75 ENHANCED PARALLEL PORT OPERATION

EPP mode provides for greater throughput and more com-

plexity than Compatible or Extended modes by supporting

faster transfer times and a mechanism that allows the host

to address peripheral device registers directly Faster trans-

fers are achieved by automatically generating the address

and data strobes EPP is compatible with both Compatible

and Extended mode parallel-port devices It consists of

eight (0 – 7) single-byte registers (See Table 7-5)

There are two EPP modes

EPP rev 17 is supported when bit 0 of PCR is 1 and bit 1 of

PCR is 0

EPP rev 19 (IEEE 1284) is supported when bit 0 of PCR is

1 and bit 1 of PCR is 1

EPP is supported for a parallel port whose base address is

278h or 378h but not for a parallel port whose base ad-

dress is 3BCh (there are no EPP registers at 3BFh) There

are four EPP transfer operations address write address

read data write and data read An EPP transfer operation is

composed of a host read or write cycle (from or to an EPP

device to an EPP register or from an EPP register to a

peripheral device)

PC87303 Datasheet(PDF) 74 Page - National Semiconductor (TI)

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