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PC87303 Datasheet(PDF) 75 Page - National Semiconductor (TI) |
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PC87303 Datasheet(HTML) 75 Page - National Semiconductor (TI) |
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75 / 114 page ![]() 70 Parallel Port (Continued) TABLE 7-5 EPP Registers Name Offset Mode Type Description Data 0 SPP RW A write to this register sets the state of the eight data pins on the 25-pin D-shell (DTR) EPP connector Status 1 SPP R A read from this register presents the system microprocessor with the real-time status (STR) EPP of five pins on the 25-pin D-shell connector and the IRQ Control 2 SPP RW A write operation to this port sets the state of four pins on the 25-pin D-shell connector (CTR) EPP and controls both the parallel port interrupt enable and direction Address 3 EPP RW A write operation to this port initiates an EPP deviceregister selection operation Data 4 EPP RW Accesses to this port initiate device read or write operations with bits 0 – 7 Port 0 Data 5 EPP RW This port is only accessed to transfer bits 8 to 15 of a 16-bit read or write to data port 0 Port 1 Data 6 EPP RW This port is only accessed to transfer bits 16 to 23 of a 32-bit read or write to data port Port 2 0 Data 7 EPP RW This port is only accessed to transfer bits 24 to 31 of a 32-bit read or write to data port Port 3 0 75 |
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