PC87303 datasheet(93/114 Pages) NSC

93 / 114 page

90 Keyboard Controller and Real-Time Clock (Continued)

the Alarm Interrupt Enable bit is set in Control Register B If

both bit 7 and bit 6 of any alarm byte (seconds alarm min-

utes alarm hours alarm) are 1 then that alarm byte is a

‘‘don’t care’’

925 RAM

The RAM data is accessed at locations 0E – 7F when

RAMSEL (bit 2) of the configuration registers is 0 and loca-

tions 00 – 7F when RAMSEL is 1 Battery backed power en-

ables the RAM to retain information during system power-

down

926 Power Management

The Power Management function provides power to the

RTC in the PC87303 During system operation power from

the system is used When system voltage falls below battery

voltage the Power Management function switches the RTC

cell to battery power For proper operation a 500 mV differ-

ential is needed between VCC and VBAT Figure 9-15 repre-

sents a typical battery configuration and

Figure 9-16 repre-

sents typical battery current during battery backed mode

TLC12074 – 50

FIGURE 9-15 Typical Battery Configuration

TLC12074 – 51

FIGURE 9-16 Typical Battery Current

during Battery Backed Mode

927 System Bus Lock Out and Power-Up Detection

As the RTC switches to battery power all inputs are locked

out so that the internal registers can not be modified This

lockout condition continues for 62 ms (min) to 125 ms (max)

after the RTC switches from battery power to system power

The 62 ms – 125 ms lockout during power transition from

battery to system power depends on the following condi-

tions

1 If the Divider Chain Control (bits 6 – 4 in Control Register

A) is in any mode but Normal Operation (010) all inputs

are enabled immediately upon detection of system volt-

age above that of battery voltage

2 When Battery voltage is below 1V and MR is 1 all inputs

are enabled immediately upon detection of system volt-

age above that of battery voltage This also initializes reg-

isters 00 through 0D to 00

3 If the VRT bit (bit 7 in Control Register D) is 0 all inputs

are enabled immediately upon detection of system volt-

age above that of battery voltage

928 Oscillator

When power is applied to the RTC in the PC87303 the

Oscillator is operational with the following exceptions

1 The VRT bit (bit 7 in Control Register D) is a 0 The oscil-

lator is disabled after initial power-up This reduces power

consumption during the time between when the battery is

initially installed and when the RTC is initialized for time-

keeping

2 The Divider Chain Control (bits 6 – 4 in Control Register A)

is in Oscillator Disabled modes (000 and 001) This pro-

vides a means for the user to ‘‘shut-down’’ the oscillator

and reduce the power consumption of the RTC cell The

RAM remains functional when the oscillator is disabled

929 Interrupt Handling

The Periodic Alarm and Update ended Interrupts are gen-

erated (IRQZ is driven low) when the respective enable bits

in Control Register B are set and an interrupt condition oc-

curs A read from Register C clears the active interrupt If a

second interrupt condition occurs (other than that which

caused the interrupt) during a read from Register C IRQZ

remains active (low) Thus it is recommended that when

multiple interrupts are enabled the interrupt service routine

continues to read (and service interrupts) until bit 7 of Con-

trol Register C (IRQ Flag) returns to a 1 Note that if an

interrupt is not serviced before a second condition of the

same interrupt occurs the second interrupt event is lost

PC87303 Datasheet(PDF) 93 Page - National Semiconductor (TI)

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