VT6516 datasheet(36/73 Pages) ETC

36 / 73 page

VIA Technologies, Inc.

Preliminary VT6516 Datarsheet

-36-

SECTION II REGISTER MAP

1. REGISTER TABLES

The VT6516 incorporates the required command/status registers and various counters for management

purposes. Although the default values of the control registers are predefined in the usual way, there is still a

requirement for CPU intervention. All registers are defined as 8 bits so that long registers have to be divided into

pieces of 8 bits with the Little-Endian principle, i.e. the lower byte in the lower address. There are only eight

registers that are directly accessible for CPU, called the CPU interface registers. They are located with memory

mapping in the range of 8000H ~ 8007H for the microprocessor 8031 in the evaluation board. The other

registers are called the internal registers that are referenced indirectly by the 16-bit address register with offset

02H ~ 03H in the CPU interface address table. While the 16-bit address register is set to reference to the specific

8-bit internal register, the following read or write operation to the 8-bit data register with offset 01H in the CPU

interface address table will cause the specified internal register to be read or written indirectly. Besides, the

address register will increase by one automatically to facilitate the successive read/write operation. If the internal

operations to them take no effect.

2 CPU INTERFACE REGISTERS MAP

*Note: register table base = 8000H for the evaluation board.

Description

Type Offset

Function

Packet Data Register

[15:0]

R/W

According to the strapping mode of packet

read/write data bus, two types are defined for 8-

bit and 16-bit data bus, respectively. For 8-bit

CPU, only the low byte of the Packet Data

CPU, the whole 16-bit Packet Data Register is

used for packet read/write.

Data Register [7:0]

R/W

The read or write operation to the 8-bit data

(referenced by the Address Register) to be read

or written indirectly.

Besides, after the read/write operation, the

Address Register will increase by one

automatically to facilitate the successive

read/write operation.

Address Register [7:0]

R/W

The low-byte address register for the reference to

an internal register with 16-bit address.

Address Register [15:8] R/W

The high-byte address register for the reference

to an internal register.

TEST Register 0 [7:0]

W/O

see the description in TEST Register 3

TEST Register 1 [7:0]

W/O

see the description in TEST Register 3

TEST Register 2 [7:0]

W/O

see the description in TEST Register 3

TEST Register 3 [7:0]

W/O

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