VT6516 datasheet(48/73 Pages) ETC

48 / 73 page

VIA Technologies, Inc.

Preliminary VT6516 Datarsheet

-48-

4C-

4FH

Congestion Factor of Output Port 15

CONGEST_F

CT15

[25:0]

R/O

50-

53H

Congestion Factor of Output Port 16 (CPU port)

There are 11 bits are used for reading FREEMCNT. Only 15 bits are

used as CPU port’s congestion factor. The read sequence of

CONGEST_FCT16[14:0] is as follows:

1. Read 0C50H to get the lowest byte.

CONGEST16[7:0] = HD[7:0]

2. Read 0C51H to get the other 7 bits.

CONGEST16[14:8] = HD[6:0]

CONGEST_F

CT16

[25:0]

R/O

4.4 Registers of Buffer Control Module

* Base Address: 1000H

Addres

(offset

)

Function

Name

Bits

Defau

Value

00-02H

Bank 0 Free Pointer

This register is initialized according to SDRAMTYPE while the

CFP is written. For 16/64Mbit SDRAM, its value is always 128

because the bank 0 free list follows the private buffer pool of buffer

entries 0~127. The free buffers with starting address at the SDRAM

even bank should be linked into this free list to improve the SDRAM

bandwidth utilization. However, if the free buffers are misplaced,

they will returned to the adequate free lists after their first release by

the output port control. Internally, the free pointer refers to the ID of

the 1st free buffer, rather than its physical address in SRAM (that is

equal to ID*3).

FREE0_PT [18:0

]

R/O

03-05H Bank 1 Free Pointer

This register is initialized according to SDRAMTYPE while the

CFP is written. For 16Mbit SDRAM, its value is 130. For 64Mbit

SDRAM, its value is 131. The fixed buffer size is 1536 bytes.

Because the page size is 2KB for 16Mbit SDRAM, the first public

buffer of bank 1 is the 130th entry located at page 1. Because the

page size is 4KB for 64Mbit SDRAM, the first public buffer of bank

1 is the 131

st entry located at page 1.

FREE1_PT [18:0

]

R/O

06-

08H

Free Memory Block Count

It is an integer value <= sizeof(SDRAM) / 1.5KB. It has to be

specified at the switch initialization stage.

To fix the bug of reading FREEMCNT in VT3061A, the bit

mapping for reading FREEMCNT is modified in VT3061B.

The write sequence of FREEMCNT is also to write data to

1006H, 1007H, 1008H. However, the read sequence of

FREEMCNT has to read data from

(1) Read 1006H to get the lowest byte, and also lock the

counter information, .i.e. FREEMCNT[7:0] = HD[7:0]

(2) Read 0C52H to get the second byte, i.e.

FREEMCNT[15:8] = HD[7:0]

(3) Read 0C53H to get the FREEMCNT[17:16]

FREEMCNT[17:16] = HD[1:0]

(4) Read 0C51H to get the FREEMCNT[18]

FREEMCNT[18] = HD[7]

FREEMC

[18:0

]

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