VT6516 datasheet(54/73 Pages) ETC

54 / 73 page

VIA Technologies, Inc.

Preliminary VT6516 Datarsheet

-54-

Addres

(offset

)

Function

Name

Bits

Defau

Value

00H

PHY ID

This is used to specify which PHY device is the objective of the

following MII commands. There are maximum 16 RMII PHY

devices.

PHYID

[3:0] 0

01H

PHY register address

In each PHY device, there are maximum 32 MII management

registers accessible by the CPU. The PHY_REG_ADDR register is

used to specify which one is the objective of the following access

command.

PHY_REG

_ADDR

[4:0] 0

02-

03H

PHY data register

Each PHY management register is 16 bits. Every data access to a

PHY management register is in unit of 16 bits, stored in this

PHYDAT

[15:0

]

04H

PHY command register

1: read

0: write

Write 0 to this register will cause a write operation to the PHY

management register (specified by the PHY_REG_ADDR) of the

PHY device (specified by the PHYID). Write 1 to this register will

cause a read operation. A read or write operation takes about 0.4 ms

so that the CPU has to read the PHYSTS register periodically to

check if the issued command is complete.

PHYCMD [0]

05H

PHY status register

2’b00: idle

2’b01: busy

2’b10: complete

This register indicates the status of the PHY control module.

Initially, the PHY control module is in the idle status. While a read

or write command is issued by writing 1/0 to the PHYCMD register,

PHYSTS becomes “busy” immediately, and goes into the

“complete” status as this operation finishes. Then, a following “read

status” command will cause it back to the “idle” status, or a

following read/write command will cause it into the “busy” status.

PHYSTS

[1:0] 0

R/O

10H

PORT0 PHY Device Address

The pair of 5-bit PHY device address and 5-bit register address

forms a unique access address to a PHY device’s register. Each PHY

device has a unique device address that is identified by the PHYID.

In the system initialization, the CPU should write PHY device

addresses, corresponding to every PHY devices, to registers

PORT[0..15]_PHY_ADDR, that may be recorded in the EEPROM

or code ROM.

PORT0_P

HY_ADD

[4:0] 0

11H

PORT1 PHY Device Address

PORT1_P

HY_ADD

[4:0] 0

12H

PORT2 PHY Device Address

PORT2_P

HY_ADD

[4:0] 0

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