VT6516 datasheet(64/73 Pages) ETC

64 / 73 page

VIA Technologies, Inc.

Preliminary VT6516 Datarsheet

-64-

02H

CPU packet read status register

2’b00: idle or packet read in progress

2’b01: packet received successfully

2’b10: packet received with error

(CPU needs to read the same packet again)

RD_PKT_

STATUS

[1:0] 0

R/O

03H

Packet source port ID

CPU can check the incoming packet’s source port

ID VIA the 3-bit register PKT_SRC_PORT before

starting to read it. It is useful to the spanning tree

algorithm.

PKT_SRC

_PORT

[3:0] 0

R/O

04H

CPU IO port configuration register

bit 0 : input port enable , 1: input enable, 0: input disable

bit 1 : output port enable , 1: output enable, 0: output disable

CPUIO_C

[1:0] 0

10H

CPU packet write status register

bits [1:0] : packet write status

2’b00: idle or packet write in progress

2’b01: CPU sent packet successfully

2’b10: CPU sent packet unsuccessfully

(CPU needs to re-write the packet again)

bit 2: CPU Input Control is ready for CPU to write packets

(It can be ready only after setting CPUIO_CFG[0] = 1.)

0: not ready (default)

1: ready

WR_PKT_

STATUS

[2:0] 0

R/O

VT6516 Datasheet(PDF) 64 Page - List of Unclassifed Manufacturers

VT6516 Datasheet(HTML) 64 Page - List of Unclassifed Manufacturers

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