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VT6516 Datasheet(PDF) 15 Page - List of Unclassifed Manufacturers

Part # VT6516
Description  16/12 PORT 10/1000 ASE T/TX
PDF  73 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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VT6516 Datasheet(HTML) 15 Page - List of Unclassifed Manufacturers

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VIA Technologies, Inc.
Preliminary VT6516 Datarsheet
-15-
See Ball
Table
EEC
O
Serial EEPROM Interface Clock Output:
EEPROM Device Addressing in the demo board:
PAGE 0 (EEPROM): Device Address = 1010 000 XXXXXXXX
PAGE 1 (EEPROM): Device Address = 1010 001 XXXXXXXX
PAGE 2 (EEPROM): Device Address = 1010 010 XXXXXXXX
PAGE 3 (EEPROM): Device Address = 1010 011 XXXXXXXX
PAGE 4 (SDRAM BANK-0): Device Address = 1010 100 XXXXXXXX
PAGE 5 (SDRAM BANK-1): Device Address = 1010 101 XXXXXXXX
See Ball
Table
EEIO
I/O
Serial EEPROM Interface Data I/O
See Ball
Table
MDC
O
Management Interface (MI) Clock Output
See Ball
Table
MDIO
I/O
Management Interface (MI) Data I/O
See Ball
Table
RCLK50
I
Main Reference Clock:
See Ball
Table
DCLK
I
SDRAM Reference Clock:
See Ball
Table
SCLK
I
SRAM Reference Clock
See Ball
Table
HCLK
O
HOST Reference Clock
HCLK is determined by the strapping pins in SYSLED[3:1], i.e. the jump
selection of J1[5-6, 3-4, 1-2]:
J1[OFF,OFF,OFF]
=> 8MHz
J1[ OFF,OFF, ON]
=> 16MHz
J1[OFF, ON, OFF]
=> 25MHz
J1[OFF, ON, ON]
=> 4MHz
J1[ ON,OFF,OFF]
=> 33MHz
See Ball
Table
RESET
I
SYSTEM RESET
See Ball
Table
SYSLED[26:0
]
O
SYSTEM Output Pins for LED:
SYSLED[8:0] are connected to pull-up IO PADs for strapping.
SYSLED[25:9] are connected to IO PADs without pull up/down.
All SYSLED[25:0] are
HOST Interface



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