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VT6516 Datasheet(PDF) 14 Page - List of Unclassifed Manufacturers |
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VT6516 Datasheet(HTML) 14 Page - List of Unclassifed Manufacturers |
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14 / 73 page ![]() VIA Technologies, Inc. Preliminary VT6516 Datarsheet -14- PIN DESCRIPTIONS No. Name Type Description SDRAM Interface See Ball Table MD[63:0] I/O SDRAM Data: 64-bit SDRAM data bus. These signals connect directly to the data input/output pins of the SDRAM devices. See Ball Table MA[11:0] O SDRAM Address Bus: 12-bit SDRAM data bus. These signals connect directly to the address input of the SDRAM devices. See Ball Table BA[1:0] O Bank Identifier for Bank 0 and 1: See Ball Table RAS [1:0] O Row Address Strobes for Bank 0 and 1: DRAM row address strobes. RAS [0] is used for Bank 0. RAS [1] is used for Bank 1. See Ball Table CAS [1:0] O Column Address Strobes for Bank 0 and 1: DRAM column address strobes. CAS [0] is used for Bank 0. CAS [1] is used for Bank 1. See Ball Table DWE [1:0] O DRAM Write Enable for Bank 0 and 1: See Ball Table DCS [3:0] O DRAM Chip Select: VT-3061A supports at most 4 SDRAM DIMM modules. SRAM Interface See Ball Table SD[31:0] I/O SRAM Data: 32-bit SRAM data bus. These signals connect directly to the data input/output pins of the SRAM devices. See Ball Table SA[17:0] O SRAM Address Bus: 18-bit SDRAM data bus. These signals connect directly to the address input of the SDRAM devices. See Ball Table SCS [4:0] O SRAM Chip Select: SRAM Type Chip Select Pins Address Pins ---------------- ---------------------- ------------------ 32KBx32 SCS[0] & SA[15] SA[14:0] 64KBx32 SCS[0] & SA[16] SA[15:0] 128KBx32 SCS[0] & SA[17] SA[16:0] 256KBx32 SCS[0] SA[17:0] See Ball Table SADS [1:0] O Synchronous Processor Address Status See Ball Table SOE [1:0] O Output Enable See Ball Table SWE [1:0] O SRAM Write Enable: Miscellaneous Interface |
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