WM8918 datasheet(29/176 Pages) CIRRUS

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Production Data

WM8918

PD, Rev 4.1, January 2012

INPUT PGA ENABLE

The input PGAs (Programmable Gain Amplifiers) and Multiplexers are enabled using register bits

INL_ENA and INR_ENA, as shown in Table 1.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R12 (0Ch)

Power

Management

INL_ENA

Left Input PGA Enable

0 = disabled

1 = enabled

INR_ENA

Right Input PGA Enable

0 = disabled

1 = enabled

Table 1 Input PGA Enable

To enable the input PGAs, the reference voltage VMID and the bias current must also be enabled.

See Reference Voltages and Master Bias for details of the associated controls VMID_RES and

BIAS_ENA.

INPUT PGA CONFIGURATION

The analogue input channels can each be configured in three different modes, which are as follows:



Single-Ended Mode (Inverting)



Differential Line Mode



Differential Mic Mode

The mode is selected by the L_MODE and R_MODE fields for the Left and Right channels

respectively. The input pins are selected using the L_IP_SEL_N and L_IP_SEL_P fields for the Left

channel and the R_IP_SEL_N and R_IP_SEL_P for the Right channel. In Single-Ended mode,

L_IP_SEL_N alone determines the Left Input pin, and the R_IP_SEL_N determines the Right Input

pin.

The three modes are illustrated in Figure 21, Figure 22 and Figure 23. It should be noted that the

available gain and input impedance varies between configurations (see also “Electrical

Characteristics”). The input impedance is constant with PGA gain setting.

The Input PGA modes are selected and configured using the register fields described in Table 2

below.

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