LPC47M182 datasheet(121/223 Pages) SMSC

121 / 223 page

Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

SMSC LPC47M182

121

Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)

DATASHEET

7.25.12 Soft Power Down Mode

This mode is entered by executing a HALT instruction. The execution of program code is halted until

either RESET is driven active or a data byte is written to the DBBIN register by a master CPU. If this

mode is exited using the interrupt, and the IBF interrupt is enabled, then program execution resumes with

a CALL to the interrupt routine, otherwise the next instruction is executed. If it is exited using RESET then

a normal reset sequence is initiated and program execution starts from program memory location 0.

7.25.13 Hard Power Down Mode

This mode is entered by executing a STOP instruction. The oscillator is stopped by disabling the

oscillator driver cell. When either RESET is driven active or a data byte is written to the DBBIN register

by a master CPU, this mode will be exited (as above). However, as the oscillator cell will require an

initialization time, either RESET must be held active for sufficient time to allow the oscillator to stabilize.

Program execution will resume as above.

7.25.14 Interrupts

The LPC47M182 provides the two 8042 interrupts: IBF and the Timer/Counter Overflow.

7.25.15 Memory Configurations

The LPC47M182 provides 2K of on-chip ROM and 256 bytes of on-chip RAM.

7.25.16 Register Definitions

Host I/F Data Register

The Input Data register and Output Data register are each 8 bits wide. A write to this 8 bit register will load

the Keyboard Data Read Buffer, set the OBF flag and set the KIRQ output if enabled. A read of this

to the KIRQ and Status register descriptions for more information.

Host I/F Status Register

The Status register is 8 bits wide.

Table 7.12 shows the contents of the Status register.

Table 7.12 - Status Register

C/D

IBF

OBF

Status Register

This register is cleared on a reset. This register is read-only for the Host and read/write by the LPC47M182

CPU.

Writable by LPC47M182 CPU. These bits are user-definable.

LPC47M182 Datasheet(PDF) 121 Page - SMSC Corporation