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LPC47M182 Datasheet(PDF) 119 Page - SMSC Corporation

Part # LPC47M182
Description  ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
PDF  223 Pages
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Manufacturer  SMSC [SMSC Corporation]
Direct Link  http://www.smsc.com
Logo SMSC - SMSC Corporation

LPC47M182 Datasheet(HTML) 119 Page - SMSC Corporation

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Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
SMSC LPC47M182
119
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
DATASHEET
Table 7.10 - I/O Address Map
ADDRESS
COMMAND
BLOCK
FUNCTION (NOTE 1)
0x60
Write
KDATA
Keyboard Data Write (C/D=0)
Read
KDATA
Keyboard Data Read
0x64
Write
KDCTL
Keyboard Command Write (C/D=1)
Read
KDCTL
Keyboard Status Read
Note 1:
These registers consist of three separate 8 bit registers. Status, Data/Command Write and Data Read.
7.25.2 Keyboard Data Write
This is an 8 bit write only register. When written, the C/D status bit of the status register is cleared to zero
and the IBF bit is set.
7.25.3 Keyboard Data Read
This is an 8 bit read only register. If enabled by “ENABLE FLAGS”, when read, the KIRQ output is cleared
and the OBF flag in the status register is cleared. If not enabled, the KIRQ and/or AUXOBF1 must be
cleared in software.
7.25.4 Keyboard Command Write
This is an 8 bit write only register. When written, the C/D status bit of the status register is set to one and
the IBF bit is set.
7.25.5 Keyboard Status Read
This is an 8 bit read only register. Refer to the description of the Status Register for more information.
7.25.6 CPU-to-Host Communication
The LPC47M182 CPU can write to the Output Data register via register DBB. A write to this register
automatically sets Bit 0 (OBF) in the Status register. See Table 7.11.
Table 7.11 - Host Interface Flags
8042 INSTRUCTION
FLAG
OUT DBB
Set OBF, and, if enabled, the KIRQ output signal goes high
7.25.7 Host-to-CPU Communication
The host system can send both commands and data to the Input Data register. The CPU differentiates
between commands and data by reading the value of Bit 3 of the Status register. When bit 3 is “1”, the
CPU interprets the register contents as a command. When bit 3 is “0”, the CPU interprets the register
contents as data. During a host write operation, bit 3 is set to “1” if SA2 = 1 or reset to “0” if SA2 = 0.



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