LPC47M182 datasheet(115/223 Pages) SMSC

115 / 223 page

Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

SMSC LPC47M182

115

Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)

DATASHEET

7.23.1 Timing Diagrams For SER_IRQ Cycle

A) Start Frame timing with source sampled a low pulse on IRQ1

SER_IRQ

PCI_CLK

Host Controller

IRQ1

Drive Source

None

IRQ0 FRAME IRQ1 FRAME

IRQ2 FRAME

None

START

START FRAME

Note:

H=Host Control; R=Recovery; T=Turn-Around; SL=Slave Control; S=Sample

Note 1: Start Frame pulse can be 4-8 clocks wide depending on the location of the device in the PCI bridge

hierarchy in a synchronous bridge design.

B) Stop Frame Timing with Host using 17 SER_IRQ sampling period

SER_IRQ

PCI_CLK

Host Controller

IRQ15

Driver

None

IRQ14

IRQ15

IOCHCK#

None

STOP

STOP FRAME

START

NEXT CYCLE

FRAME

Note:

H=Host Control; R=Recovery; T=Turn-Around; S=Sample; I=Idle

Note 1: The next SER_IRQ cycle’s Start Frame pulse may or may not start immediately after the turn-

around clock of the Stop Frame.

Note 2: There may be none, one or more Idle states during the Stop Frame.

Note 3: Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode.

7.23.2 SER_IRQ Cycle Control

There are two modes of operation for the SER_IRQ Start Frame:

1) Quiet (Active) Mode: Any device may initiate a Start Frame by driving the SER_IRQ low for one clock,

while the SER_IRQ is Idle. After driving low for one clock the SER_IRQ must immediately be tri-stated

without at any time driving high. A Start Frame may not be initiated while the SER_IRQ is Active. The

SER_IRQ is Idle between Stop and Start Frames. The SER_IRQ is Active between Start and Stop

Frames. This mode of operation allows the SER_IRQ to be Idle when there are no IRQ/Data transitions

which should be most of the time.

Once a Start Frame has been initiated the Host Controller will take over driving the SER_IRQ low in the

next clock and will continue driving the SER_IRQ low for a programmable period of three to seven clocks.

This makes a total low pulse width of four to eight clocks. Finally, the Host Controller will drive the

SER_IRQ back high for one clock, then tri-state.

LPC47M182 Datasheet(PDF) 115 Page - SMSC Corporation

LPC47M182 Datasheet(HTML) 115 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL