LPC47M182 datasheet(114/223 Pages) SMSC

114 / 223 page

Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)

114

SMSC LPC47M182

DATASHEET

Note: A threshold of 16 is equivalent to a threshold of 15. These two cases are treated the same.

7.21.4 Programmed I/O - Transfers from the FIFO to the Host

In the reverse direction an interrupt occurs when serviceIntr is 0 and readIntrThreshold bytes are

available in the FIFO. If at this time the FIFO is full it can be emptied completely in a single burst,

otherwise readIntrThreshold bytes may be read from the FIFO in a single burst.

readIntrThreshold =(16-<threshold>) data bytes in FIFO

An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is greater than or

equal to (16-<threshold>). (If the threshold = 12, then the interrupt is set whenever there are 4-16 bytes in

the FIFO). The host must respond to the request by reading data from the FIFO. This process is repeated

until the last byte is transferred out of the FIFO. If at this time the FIFO is full, it can be completely emptied

in a single burst, otherwise a minimum of (16-<threshold>) bytes may be read from the FIFO in a single

burst.

7.21.5 Programmed I/O - Transfers from the Host to the FIFO

In the forward direction an interrupt occurs when serviceIntr is 0 and there are writeIntrThreshold or more

bytes free in the FIFO. At this time if the FIFO is empty it can be filled with a single burst before the empty

bit needs to be re-read. Otherwise it may be filled with writeIntrThreshold bytes.

writeIntrThreshold

(16-<threshold>) free bytes in FIFO

An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is less than or equal to

<threshold>. (If the threshold = 12, then the interrupt is set whenever there are 12 or less bytes of data in

the FIFO.) The host must respond to the request by writing data to the FIFO. If at this time the FIFO is

empty, it can be completely filled in a single burst, otherwise a minimum of (16-<threshold>) bytes may be

written to the FIFO in a single burst. This process is repeated until the last byte is transferred into the

FIFO.

7.22

Power Management

Direct power management capability is provided for the following logical devices: floppy disk, UART, and

the parallel port. Direct power management is controlled by CR22. Refer to CR22 in Table 11.3 for more

information.

Note on FDC Direct Powerdown: The Direct powerdown mode requires at least 8us delay at 250K

bits/sec configuration and 4us delay at 500K bits/sec. The delay should be added so that the

internal microcontroller can prepare itself to accept commands.

7.23

Serial IRQ

The LPC47M182 supports the serial interrupt to transmit interrupt information to the host system. The

serial interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0.

LPC47M182 Datasheet(PDF) 114 Page - SMSC Corporation

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