LPC47M182 datasheet(116/223 Pages) SMSC

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Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)

116

SMSC LPC47M182

DATASHEET

If LPC47M182 detects any transition on an IRQ/Data line for which it is responsible, it initiates a Start

Frame in order to update the Host Controller unless the SER_IRQ is already in an SER_IRQ Cycle and the

IRQ/Data transition can be delivered in that SER_IRQ Cycle

2) Continuous (Idle) Mode: Only the Host controller can initiate a Start Frame to update IRQ/Data line

information. All other SER_IRQ agents become passive and may not initiate a Start Frame. SER_IRQ will

be driven low for four to eight clocks by Host Controller. This mode has two functions. It can be used to

stop or idle the SER_IRQ or the Host Controller can operate SER_IRQ in a continuous mode by initiating a

Start Frame at the end of every Stop Frame.

An SER_IRQ mode transition can only occur during the Stop Frame. Upon reset, SER_IRQ bus is

defaulted to Continuous mode, therefore only the Host controller can initiate the first Start Frame. Slaves

must continuously sample the Stop Frames pulse width to determine the next SER_IRQ Cycle’s mode.

7.23.3 SER_IRQ Data Frame

Once a Start Frame has been initiated, the LPC47M182 will watch for the rising edge of the Start Pulse

and start counting IRQ/Data Frames from there. Each IRQ/Data Frame is three clocks: Sample phase,

Recovery phase, and Turn-around phase. During the Sample phase the LPC47M182 drives the SER_IRQ

low, if and only if, its last detected IRQ/Data value was low. If its detected IRQ/Data value is high,

SER_IRQ is left tri-stated. During the Recovery phase the LPC47M182 drives the SER_IRQ high, if and

only if, it had driven the SER_IRQ low during the previous Sample Phase. During the Turn-around Phase

the LPC47M182 tri-states the SER_IRQ. The LPC47M182 drives the SER_IRQ line low at the appropriate

sample point if its associated IRQ/Data line is low, regardless of which device initiated the Start Frame.

The Sample Phase for each IRQ/Data follows the low to high transition of the Start Frame pulse by a

number of clocks equal to the IRQ/Data Frame times three, minus one. (e.g. The IRQ5 Sample clock is

the sixth IRQ/Data Frame, (6 x 3) - 1 = 17

th clock after the rising edge of the Start Pulse).

SER_IRQ Sampling Periods

SER_IRQ PERIOD

SIGNAL SAMPLED

# OF CLOCKS PAST START

Not Used

IRQ1

IRQ2

IRQ3

IRQ4

IRQ5

IRQ6

IRQ7

IRQ8

IRQ9

IRQ10

IRQ11

IRQ12

IRQ13

IRQ14

IRQ15

SER_IRQ Period 14 is used to transfer IRQ13. Logical devices FDC, Parallel Port, Serial Port, and Keyboard have

IRQ13 as a choice for their primary interrupt.

LPC47M182 Datasheet(PDF) 116 Page - SMSC Corporation

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