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LPC47M182 Datasheet(PDF) 128 Page - SMSC Corporation |
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LPC47M182 Datasheet(HTML) 128 Page - SMSC Corporation |
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128 / 223 page  Advanced I/O Controller with Motherboard GLUE Logic Datasheet Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) 128 SMSC LPC47M182 DATASHEET Table 7.16 – GPIO Summary DEFAULT FUNCTION ALT FUNC 1 ALT FUNC 2 PWR WELL PCI RESET VCC POR VTR POR PME/EETI nCDC_DWN _ENAB GP24 - VTR - - Input - GP10 - - VTR - - Input PME GP11 - - VTR - - Input PME GP12 - - VTR - - Input PME GP13 - - VTR - - Input PME GP14 - - VTR - - Input PME GP15 - - VTR - - Input PME GP16 FAN_TACH1 (Note 1) - VTR - - Input PME GP17 FAN_TACH2 (Note 1) - VTR - - Input PME DDCSDA_5V GP20 EETI0 VTR Note 1 - - Hi-Z PME/EETI DDCSCL_5V GP21 EETI1 VTR Note 1 - - Hi-Z PME/EETI DDCSDA_3V GP22 - VTR Note 1 - - Hi-Z PME DDCSCL_3V GP23 - VTR Note 1 - - Hi-Z PME Note 1: When DDC functions are selected, these pins require external pull-ups to appropriate voltages. 7.27.2 Description Each GPIO port has a 1-bit data register and an 8-bit configuration control register. The data register for each GPIO port is represented as a bit in one of the 8-bit GPIO DATA Registers, GP1 to GP2. The bits in these registers reflect the value of the associated GPIO pin as follows. Pin is an input: The bit is the value of the GPIO pin. Pin is an output: The value written to the bit goes to the GPIO pin. Latched on read and write. All of the GPIO registers are located in the GPIO/Runtime Register logical device (see “GPIO Runtime Registers” section when LD_NUM=0 and “Runtime Register Block Runtime Registers” section when LD_NUM=1). The GPIO ports with their alternate functions and configuration state register addresses are listed in Table 7.17. Table 7.17 – General Purpose I/O Port Assignments DEFAULT FUNCTION ALT. FUNC. 1 ALT. FUNC. 2 DATA REGISTER 1 DATA REGISTER BIT NO. GPIO RUNTIME REGISTER OFFSET (HEX) nCDC_DWN_ENAB GP24 - 0 GP10 - - 1 GP11 - - 2 GP12 - - 3 GP13 - - 4 GP14 - - 5 GP15 - - 6 GP16 FAN_TACH1 - GP1 7 15 GP17 FAN_TACH2 - GP2 0 16 |
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