LPC47M182 datasheet(129/223 Pages) SMSC

129 / 223 page

Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

SMSC LPC47M182

129

Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)

DATASHEET

DEFAULT

FUNCTION

ALT. FUNC. 1

ALT. FUNC. 2

DATA

BIT NO.

GPIO

RUNTIME

OFFSET

(HEX)

DDCSDA_5V

GP20

EETI0

DDCSCL_5V

GP21

EETI1

DDCSDA_3V

GP22

DDCSCL_3V

GP23

Reserved

7:5

Note 1:

The GPIO Data and Configuration Registers are located in GPIO/Runtime Register block at the offset

shown from the GPIO/Runtime Register Block logical device base address.

7.27.3 GPIO Control

Each GPIO port has an 8-bit control register that controls the behavior of the pin. (See “GPIO Runtime

Registers” section when LD_NUM=0 and “Runtime Register Block Runtime Registers” section when

LD_NUM=1).

Each GPIO port may be configured as either an input or an output. If the pin is configured as an output, it

can be programmed as open-drain or push-pull. Inputs and outputs can be configured as non-inverting or

inverting. Bit[0] of each GPIO Configuration Register determines the port direction, bit[1] determines the

signal polarity, and bit[7] detemines the output driver type select.

The Polarity Bit (bit 1) of the GPIO control registers control the GPIO pin when the pin is configured for the

GPIO function and when the pin is configured for the alternate function for all pins, with the exception of

the either edge triggered interrupts and DDC functions.

The basic GPIO configuration options are summarized in Table 7.18.

Table 7.18 – GPIO Configuration Summary

SELECTED

FUNCTION

DIRECTION

BIT

POLARITY

BIT

DESCRIPTION

Pin is a non-inverted output.

Pin is an inverted output.

Pin is a non-inverted input.

GPIO

Pin is an inverted input.

LPC47M182 Datasheet(PDF) 129 Page - SMSC Corporation

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