LPC47M182 datasheet(108/223 Pages) SMSC

108 / 223 page

Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)

108

SMSC LPC47M182

DATASHEET

7.12.7 cnfgA (Configuration Register A)

ADDRESS OFFSET = 400H

Mode = 111

This register is a read only register. When read, 10H is returned. This indicates to the system that this is an

8-bit implementation. (PWord = 1 byte)

7.12.8 cnfgB (Configuration Register B)

ADDRESS OFFSET = 401H

Mode = 111

BIT 7 compress

This bit is read only. During a read it is a low level. This means that this chip does not support hardware

RLE compression. It does support hardware de-compression.

BIT 6 intrValue

Returns the value of the interrupt to determine possible conflicts.

BIT [5:3] Parallel Port IRQ (read-only)

to Table 7.7

BITS [2:0] Parallel Port DMA (read-only)

to Table 7.8

7.12.9 ecr (Extended Control Register)

ADDRESS OFFSET = 402H

Mode = all

This register controls the extended ECP parallel port functions.

BITS 7,6,5

These bits are Read/Write and select the Mode.

BIT 4 nErrIntrEn

Read/Write (Valid only in ECP Mode)

Disables the interrupt generated on the asserting edge of nFault.

Enables an interrupt pulse on the high to low edge of nFault. Note that an interrupt will be

generated if nFault is asserted (interrupting) and this bit is written from a 1 to a 0. This prevents interrupts

from being lost in the time between the read of the ecr and the write of the ecr.

BIT 3 dmaEn

Read/Write

Enables DMA (DMA starts when serviceIntr is 0).

Disables DMA unconditionally.

BIT 2 serviceIntr

Read/Write

Disables DMA and all of the service interrupts.

Enables one of the following 3 cases of interrupts. Once one of the 3 service interrupts has

occurred serviceIntr bit shall be set to a 1 by hardware. It must be reset to 0 to re-enable the interrupts.

Writing this bit to a 1 will not cause an interrupt.

LPC47M182 Datasheet(PDF) 108 Page - SMSC Corporation

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