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MFC2000 Datasheet(PDF) 309 Page - List of Unclassifed Manufacturers |
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MFC2000 Datasheet(HTML) 309 Page - List of Unclassifed Manufacturers |
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309 / 426 page ![]() Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 100723A Conexant 16-11 Address: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: USBEP3Tran (W) $01FF85BF Ep3 Transition Register Address: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: USBEP3Tran (W) $01FF85BE Ep3 Transition Register Bit 15-0: Not used Writing any value to this register causes a push or pop of data through the FIFO data port and the FIFO Quad Halfword 1-4 registers. The FIFO operation depends on the direction of data flow. If system bus (CPU or DMA) is writing (filling) the FIFO, data is transferred from the FIFO data port register to the FIFO Quad Halfword 1 register, simultaneously with data transfer from Quad Halfword 1 to Quad Halfword 2, Quad Halfword 2 to Quad Halfword 3, and Quad Halfword 3 to Quad Halfword 4, with the original data of Quad Halfword 4 being lost. If the system bus is reading (emptying) the FIFO, data is transferred from the FIFO Quad Halfword 1 register to the FIFO data port register, simultaneously with data transfer from Quad Halfword 2 to Quad Halfword 1, Quad Halfword 3 to Quad Halfword 2, and Quad Halfword 4 to Quad Halfword 3, with the contents of Quad Halfword 4 becoming indeterminate. Address: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: USBEP4Fifo1 (R) $01FF85C1 EP4 Fifo Half Word 1 Reset. Value 00h Read Value 00h Address: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: USBEP4Fifo1 (R) $01FF85C0 EP4 Fifo Half Word 1 Reset. Value 00h Read Value 00h Bits 15-0: Endpoint 4 FIFO Quad Half word 1 |
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