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MFC2000 Datasheet(PDF) 312 Page - List of Unclassifed Manufacturers

Part # MFC2000
Description  Multifunctional Peripheral Controller 2000
PDF  426 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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MFC2000 Datasheet(HTML) 312 Page - List of Unclassifed Manufacturers

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MFC2000 Multifunctional Peripheral Controller 2000
Hardware Description
16-14
Conexant
100723A
Bit 5:
This bit indicates that there is a single byte in the holding register.
Bit 4-2:
This bit field indicates the number of quad halfwords that contain data.
Valid values are from 0 to 4.
Bit 1-0:
This bit field indicates which byte of the FIFO quad halfword structure
is the next to receive input data.
Address:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Default:
USBEP4Data
(R/W)
$01FF85CD
EP4 Endpoint Dataport Register
Reset Value
00h
Read Value
00h
Address:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default:
USBEP4Data
(R/W)
$01FF85CC
EP4 Endpoint Dataport Register
Reset Value
00h
Read Value
00h
Bits 15-0:
Endpoint 4 FIFO Data Port Register
Address:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Default:
USBEP4Tran
(W)
$01FF85CF
EP4 Transition Register
Address:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default:
USBEP4Tran
(W)
$01FF85CE
EP4 Transition Register
Bit 15-0:
Not used
Writing any value to this register causes a push or pop of data through
the FIFO data port and the FIFO Quad Halfword 1-4 registers. The
FIFO operation depends on the direction of data flow. If system bus
(CPU or DMA) is writing (filling) the FIFO, data is transferred from the
FIFO data port register to the FIFO Quad Halfword 1 register,
simultaneously with data transfer from Quad Halfword 1 to Quad
Halfword 2, Quad Halfword 2 to Quad Halfword 3, and Quad Halfword
3 to Quad Halfword 4, with the original data of Quad Halfword 4 being
lost. If the system bus is reading (emptying) the FIFO, data is
transferred from the FIFO Quad Halfword 1 register to the FIFO data
port register, simultaneously with data transfer from Quad Halfword 2
to Quad Halfword 1, Quad Halfword 3 to Quad Halfword 2, and Quad
Halfword 4 to Quad Halfword 3, with the contents of Quad Halfword 4
becoming indeterminate.



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