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MFC2000 Datasheet(PDF) 369 Page - List of Unclassifed Manufacturers |
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MFC2000 Datasheet(HTML) 369 Page - List of Unclassifed Manufacturers |
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369 / 426 page ![]() Multifunctional Peripheral Controller 2000 MFC2000 100723A Conexant 21-1 21. Pwm Logic 21.1 Functional Description There are five PWM channels, each channel having separate logic and control. PWM channel 0 outputs from the GPIO[11]/CPCIN pin. There is a PWMCh0 select bit in the PWMCh0Duty Register. The PWMCh0 select bit goes to the GPIO block where the signal selection and the prioritization for the GPIO[11]/CPCIN/PWM0 pin is done. PWM channel 1 and PWM channel 2 share pins with FCS[0]n and FCS[1]n. There is a PWMCh1 select bit in the PWMCh1Duty Register. There is a PWMCh2 select bit in the PWMCh2Duty Register. PWM channel 3 shares the pin with GPIO[5]/CS[3]n. There is a PWMCh3 select bit in the PWMCh3Duty Register. The PWMCh3 select bit goes to the GPIO block where the signal selection and the prioritization for the GPIO[5]/CS[3]n/PWM3 pin is done. PWM channel 4 shares the pin with GPIO[10]/P80_PB3. There is a PWMCh4 select bit in the PWMCh4Duty Register. The PWMCh4 select bit goes to the GPIO block. The GPIO logic does the signal selection and the prioritization for the GPIO[10]/P80_PB3/PWM4 pin. The PWM function requirements are as follows. • Signal frequency range " AUXCLK/256 or AUXCLK/(2*256) • Duty cycle " high level: 1/256 to 256/256 • 8-bit counter for duty cycle programmability |
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