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MFC2000 Datasheet(PDF) 371 Page - List of Unclassifed Manufacturers |
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MFC2000 Datasheet(HTML) 371 Page - List of Unclassifed Manufacturers |
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371 / 426 page ![]() Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 100723A Conexant 21-3 Name/Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default PWM Channel 1 Control (PWMCh1Ctrl) 01FF80C3h PWMCh1 Output Select (not used) (not used) (not used) (not used) (not used) (not used) PWMCh1 Clock Divider Rst. Value 0xxxxxx0b Read Value 0xxxxxx0b Name/Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default PWM Channel 1 Control (PWMCh1Ctrl) 01FF80C2h Bit 7 of PWMCh1 Duty Cycle Control Bit 6 of PWMCh1 Duty Cycle Control Bit 5 of PWMCh1 Duty Cycle Control Bit 4 of PWMCh1 Duty Cycle Control Bit 3 of PWMCh1 Duty Cycle Control Bit 2 of PWMCh1 Duty Cycle Control Bit 1 of PWMCh1 Duty Cycle Control Bit 0 of PWMCh1 Duty Cycle Control Rst. Value 00h Read Value 00h Bit 15 Controls which signal is output to the FCS[0]n pin (PWM channel 1 output signal or the other output signal). Bit 8/FlashCtrl Register Bit 15/PWMCh1Ctrl Register FCS[0]n/PWM1 Pin 00 FCS[0] 01 FCS[0] 1 0 FCS[0] for NAND-type Flash Mem 11 PWM1 Bit 8 PWMCh1 clock divider (n = 0-1) PWMCh1 clock = AUXCLK n () + 1 Bits 7-0 Duty cycle control (n = 0 - 255) PWMCh1 signal frequency = PWMCh clock 1 256 PWMCh1 signal ‘high’ period = n + 1 256 * PWMCh1 signal cycle time PWMCh1 signal ‘low’ period = 256 1 256 −+ () n * PWMCh1 signal cycle time |
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