MFC2000 datasheet(408/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

24-22

Conexant

100723A

24.6 VIDEO/SCANNER INTERFACE

24.6.1 Function Description

The Video/Scan Interface connects the Video/Scan Controller to the SDRAM via DMA cycles. This interface has a

unidirectional data flow: Video/Scan Controller to SDRAM. It consists of two 64 halfword buffers that ping-pong,

address counters for Video/Scan Controller input, and CDRAM output and byte to halfword assembly.

The Video/Scan Controller transmits a single line when attached to the scanner input or a single frame when

attached to the video input. In either case, the Video/Scan Controller data flow is as follows:

The Video/Scan Controller initiates a transfer by a single high-going pulse on the start signal to VSI .

As each analog sample becomes available, it is placed on the VSC output bus and the data ready signal is

pulsed high to VSI. In the case of video capture, it is expected that the data ready signal will remain high for

long periods of time as video data is available at each rising edge of the data clock. In the case of scanner

capture, it is expected that the data ready signal will be inactive for several data clocks between successive

pixels.

As the Video/Scan Interface receives data from the Video/Scan Controller, it is assembled into halfwords and

then stored into one of the two ping-pong buffers. When the buffer is filled, data storing is switched to the

remaining buffer and a signal is passed to the opposite side of the interface indicating a buffer is available for

transfer.

The Video/Scan Controller terminates the transfer by a single high-going pulse on the stop signal.

On the Countach Bus Subsystem side of the Video/Scan Interface, the data flow is as follows:

A pulse is received from the Video/Scan Controller side of the Video/Scan Interface indicating a buffer is

available for transfer.

VSI asserts the DMA request signal to CBU. The sequencial DMA signal is also asserted if the buffer contains

more than one halfword of data.

Once the DMA acknowledge signal is detected, transfer begins, one data being transferred for each SDRAM

ready pulse.

24.6.2 Register Description

Address:

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default:

Video/Scanner

Interface Mode

(VSIMode)

$01FF8289

(Not Used)

Rst. Value

xxh

Read Value

00h

Address:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default:

Video/Scanner

Interface Mode

(VSIMode)

$01FF8288

(Not Used)

Video/Scanner

DMA Hog

Mode[1]

Video/Scanner

DMA Hog

Mode[0]

Rst Value

xxxxxx00b

Read Value

00h

Bit 15-2

Not used

Bit 1-0

The Video/Scanner DMA Hog Mode field is used to throttle and/or

disable other DMA masters during video capture. It has the following

settings:

Hog Mode

Countach Subsystem Interface

Arm Bus Interface

Burst and single DMA allowed

No burst – single DMA only

No DMA allowed

No burst – single DMA only

No DMA allowed

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