MFC2000 datasheet(410/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

24-24

Conexant

100723A

24.7.1.1 Memory Bank Structure

There will only be one bank of memory allowed. Accesses to those banks must be done as halfword (16 bit)

accesses. SDRAM with 8-bit data bus will not be byte addressable as far as the system in concerned. Instead,

each 16-bit access will write or read two consecutive bytes of data to/from the 8-bit SDRAM. For instance, a

request to access to byte location 0x100 or 0x101 in 8-bit SDRAM will both access the same halfword (16-bit)

location. Hardware does NOT support byte access to external memory connected to (S)DRAM.

24.7.1.2 Wait State Profile

50 ns FPDRAM read requests will have two 25Mhz wait states for the first read access and zero wait states for

each successive read. So the FPDRAM read wait state profile is considered to be 2-0-0-0. For example, a burst of

four reads will take six cycles to complete; three for the first read, and three total for the next three reads. For

60ns FPDRAM, the read wait state profile is 2-0-1-0-1-0, etc.

The write wait state profile for 50ns FPDRAM is 1-0-0-0. The write wait state profile for 60 ns FPDRAM is

1-0-1-0-, etc.

SDRAMs will have an identical wait state profile regardless of whether they use a 16 bit data bus or 8 bit data

bus. Writes will have a profile of 1-0-0-0. Reads will have a wait state profile of 2-0-0-0. In either case when the

burst or single access is finished, there will be a 1 cycle penalty in order to satisfy Trc.

24.7.1.3 Address Multiplexing

When reading chart, note that the address bits and data bit on the leftmost column correspond to the actual bits

which are output of the (S)DRAMC block (also outputs of ASIC), whereas the address bits in the row/col columns

correspond to the input addresses to the (S)DRAMC block (which are aligned to halfword boundary). In other

words, the address requested by CBU will be a halfword address, not a byte address. As a result, the CBU and

(S)DRAMC will communicate via a 22-bit address bus.

In the following charts, MA[x] refers to the memory address pin located on the MFC2000 ASIC (i.e.,. cdao[x]).

MD[x] refers to the memory data pin located on the MFC2000 ASIC (i.e.,cddo[x]).

BA[x] refers to the bank pin on the SDRAM part. EA[x] refers to the external address pin located on the RAM part.

So the External address column of the chart shows the actual connection between the MFC2000 and the RAM.

(i.e., looking at the first row of the chart, there will be a wire connecting MA[12] of the MFC2000 to the BA1 of

the SDRAM).

A[x], within the ROW/COL columns of the chart, refers to the 22-bit address bus within the chip

MFC2000 Datasheet(PDF) 410 Page - List of Unclassifed Manufacturers