MFC2000 datasheet(414/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

24-28

Conexant

100723A

24.8 Register Description

Name/Address

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default

DRAM

Configuration

0x01FF8281

Rst. Value

‘h00

Read Value

‘h00

Name/Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

DRAM

Configuration

0x01FF8280

CDRAM

Clock Enable

Configuration Code

Rst. Value

‘h00

Read Value

‘h00

This register contains the information necessary to decide whether DRAM or SDRAM is being used, the size of

memory being used, and whether an 8- or 16-bit DRAM is being used. This register should be written to ONCE

and only once as the CDRAM may not work properly if this is written to a second or more times. In

addition, most RAMs require a minimum of 100us delay before use in order for the RAM to stabilize, but some

others require more time. To properly use the RAM, this register should be written to ONLY after the appropriate

delay for that particular RAM is met. Writing to this register will cause the CDRAM to perform the proper ammount

of refreshes, the precharge, and mode set necessary for correct startup of DRAM or SDRAM.

Bit 15-5

Bit 4

CDRAM Clock Enable

This bit enables or disables the CDRAM external clock. When

using FPDRAM, the clock does not need to be enabled.

0: Enable

1: Disable

Bit 3-0

DRAM Type

Configuration Code

SDRAM 8-bit 16 Mb

0010

SDRAM 8-bit 64 Mb

0110

SDRAM 16-bit 16 Mb

0000

SDRAM 16-bit 64 Mb

0100

FPDRAM 60ns 16 Mb (10x10)

0111

FPDRAM 60ns 16 Mb (12x8)

0011

FPDRAM 60ns 64 Mb (12x10)

0111

FPDRAM 50ns 16 Mb (10x10)

1111

FPDRAM 50ns 16 Mb (12x8)

1011

FPDRAM 50ns 64 Mb (12x10)

1111

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