MFC2000 datasheet(409/426 Pages) ETC

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Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

24-23

24.6.3 Internal Memory

The Video/Scanner Interface contains two 64x16 buffers for DMA transfers from the Video/Scanner Controller and

the Countach SDRAM. The buffers can be accessed by the ARM as halfwords only.

The two buffers are located at the following address:

Ping pong buffer 1: $01FFA400

$01FFA47F

Ping pong buffer 2: $01FFA480

$01FFA4FF

ARM access to the VSI buffers is provided for diagnostic purposes only and should not be used as part of normal

operation. When the ARM makes an access to the buffers, the ARM is held off and clock domain synchronization

occurs before the access is completed. As a result, a significant wait state penalty is incurred.

24.7 (S)DRAM Controller ((S)DRAMC)

24.7.1 Function Description

The (S)DRAM Controller is used to communicate between the Countach Bus Unit (CBU) and external FPDRAM

or SDRAM memory. This memory will primarily be used for reading and writing large amounts of sequential data

necessary for carrying out the programs running on the Countach Imaging DSP core. Whether DRAM or SDRAM

is used is an option, but only one memory unit is accessible to the memory controller.

The (S)DRAMC state machine uses a 100Mhz or 87.5Mhz clock to control the SDRAM and DRAM. The CBU will

communicate with (S)DRAMC at 25 Mhz or 21.875Mhz, so all data received from either RAM type must be

synchronized to this speed before sent to the CBU. A third clock, an inverted version of the 100Mhz or 87.5Mhz

clock, will be sent to the SDRAM memory. In this document, 100Mhz clock will be used for all descriptions. From

the timing point of view, 87.5Mhz will be covered if it meets 100Mhz requirements.

The supported DRAM characteristics are listed in the following table:

Table 24-4: Supported FPDRAM Chip Characteristics

Addressing Size:

2 MB, 8 MB

Organization:

16 bits

Access Speed:

50 ns, 60 ns

Table 24-5: Supported SDRAM Chip Characteristics

Addressing Size:

2 MB, 8 MB

Organization:

8 bits or 16 bits

Access Speed:

10 ns

The maximum memory size that is supported for either memory type is 8MB. Six possible row/column pinouts

types are supported. A more detailed description can be found in the address multiplexing table.

SDRAM will always be used in burst mode, with one access per burst. The CAS latency will be set to 3 cycles

which is normal for SDRAM running at 100MHz. The two possible sizes and two possible organizations are

programmable in the (S)DRAMC control register.

Fast page mode DRAMs (50ns and 60ns) are supported. The speed requirement is due to the bandwidth

requirements of the Countach Imaging DSP. The DRAMS will be used in both fast page burst mode and single

access mode. The two possible densities which are supported are programmable in the (S)DRAMC control

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