MFC2000 datasheet(131/426 Pages) ETC

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Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

5-5

5.1.3

External Reset (RESETn) and Watchdog Reset

A driver on the AMPFC's RESETn pin provides a reset signal to external devices whenever the internal

Battrtc_RESn or watchdog reset is active (low). This pin also includes an input driver that allows external control

circuitry to reset the CPU and all VDD powered registers (including a power-down SYSIRQ condition). The

external RESETn and internal RESn are also activated when the watchdog timer times out (refer to the watchdog

timer section that follows).

An externally generated reset does not affect the battery powered registers nor DRAM refresh operation.

[CAUTION] Don’t drive the RESETn pin ‘high’ from external. Only drive the RESETn pin ‘low’ to generate the

reset from external and don’t drive the RESETn pin when external reset is not needed.

5.1.4

Power Reset Timing Diagram

The battery and VDD power on reset timing is illustrated in Figure 5-1. The first event shown is the battery voltage

and lockout rising together as battery voltage is applied, followed by BATRSTn going high, and the start up of

XOUT. On the second falling edge of Reset clock after VDD has been applied and PWRDWNn has been driven

high, Battrtc_RESn goes high and approximately eight SIUCLKs are counted as Power-Up Delay 2. At the

completion of eight SIUCLKs, battery lockout is removed allowing access to the BackupConfig register.

Internal clock on

PWRDWNn

Power up

Delay 1

(125-250ms)

Power up

Delay 2 (8 SIUCLKs)

8 SIUCLKs)

(internal) SIUCLK

(internal) Reset

Clock - 125ms

Battery Voltage

Lockout

BATRSTn

VDD

(internal)

Battrtc_RESn

RESETn

(internal) RESn

(internal)

clock enable

Figure 5-3. Power Reset Timing Diagram

MFC2000 Datasheet(PDF) 131 Page - List of Unclassifed Manufacturers

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