MFC2000 datasheet(134/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

5-8

Conexant

100723A

Bit 8:

Bank 0 Interface Size

This register defines whether the databus to the bank 0 DRAMs is 8

bits wide or 16 bits wide. An 8-bit wide DRAM interface uses RASn[0]

and CASOn[0]. A 16-bit wide non-interleaved DRAM interface uses

RASn[0] and CASOn[1:0]. A 16-bit wide interleaved DRAM interface

uses RASn[0], CASEn[1:0], and CASOn[1:0].

Bits 7-6:

DRAM Battery Backup Time

These bits control the amount of time that the DRAM controller will

spend refreshing the DRAMs when in the battery backup mode. After

reset when the CPU is being released to run, the CPU will not be able

to write data to bits 7 and 6 of the BackupConfiguration register

immediately since the immediate write will not take effect. The CPU

must wait at least one oscillator clock cycle before writing data into bits

7 and 6.

Bit 7

Bit 6

Battery Backup Duration:

No battery backup

1-2 days

2-3 days

Infinite

Bit 5-4:

DRAM Refresh Rate

These bits are used to set up the DRAM refresh rate. See the

following table:

Refresh

Speed:

(bit 5)

Oscillator

Speed:

(bit 4)

Refresh

Speed:

Description:

normal

RTC crystal frequency = 32.768 kHz,

Refresh clock = the crystal frequency= 32.768 kHz,

The refresh cycle time = 15.625 ms/1024 cycles.

fast

RTC crystal frequency = 65.536 kHz,

Refresh clock = the crystal frequency = 65.536 kHz,

Refresh cycle time = 7.8125 ms/1024 cycles.

slow

RTC crystal frequency = 32.768 kHz,

Refresh clock = the crystal frequency/8 = 4.096 kHz

Refresh cycle time = 125 ms/1024 cycles.

slow

RTC crystal frequency = 65.536 kHz,

Refresh clock = the crystal frequency/16 = 4.096 kHz

Refresh cycle time = 125 ms/1024 cycles.

Bits 3:

Bank 1 Enable

This bit controls whether or not the Bank 1 DRAMs will be enabled.

The Enable signal will allow CAS before RAS refresh to occur based

on the non-interleave or interleave setting. If the bank setting indicates

a non-interleaved mode, RASn[1] and CASOn[0] (8-bit mode) or

CASOn[1:0] (16-bit mode) will refresh the DRAM. If the bank setting

indicates an interleaved mode, RASn[1], CASOn[1:0] and CASEn[1:0]

will refresh the DRAM. DWRn will be high during refresh. CASEn[1:0]

will be tristated if Bank 0 is in non-interleaved mode. If this bit is set to

a zero, RASn[1] will be tristated. Default disabled.

MFC2000 Datasheet(PDF) 134 Page - List of Unclassifed Manufacturers

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